diff options
author | James Hogan <james.hogan@imgtec.com> | 2017-07-18 12:55:56 +0100 |
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committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-07-20 22:42:26 +0100 |
commit | cec56a733dd2c3fa81dbedbecf03922258747f7d (patch) | |
tree | c8cac93783b4fd91c05c7ef2ef58b958961be694 /target/mips/op_helper.c | |
parent | 42c86612d507c2a8789f2b8d920a244693c4ef7b (diff) | |
download | qemu-cec56a733dd2c3fa81dbedbecf03922258747f7d.tar.gz |
target/mips: Add segmentation control registers
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.
Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/op_helper.c')
-rw-r--r-- | target/mips/op_helper.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c52a407e86..526f8e4969 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1322,6 +1322,30 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) restore_pamask(env); } +void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs = CPU(mips_env_get_cpu(env)); + + env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; + tlb_flush(cs); +} + +void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs = CPU(mips_env_get_cpu(env)); + + env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; + tlb_flush(cs); +} + +void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs = CPU(mips_env_get_cpu(env)); + + env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; + tlb_flush(cs); +} + void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { if (env->insn_flags & ISA_MIPS32R6) { |