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| author | Richard Henderson <rth@twiddle.net> | 2016-11-16 11:11:54 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:11 -0800 |
| commit | 1a0196c5c7f197fad7b079074d587b3204bcfb0f (patch) | |
| tree | 2feec0bfff244fabb46dfe5f896aae846b1c54b2 /target/mips | |
| parent | 5318420c62b6f6ce0bb7cfcf115fc21055015f90 (diff) | |
| download | qemu-1a0196c5c7f197fad7b079074d587b3204bcfb0f.tar.gz | |
target-mips: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/helper.h | 7 | ||||
| -rw-r--r-- | target/mips/op_helper.c | 22 | ||||
| -rw-r--r-- | target/mips/translate.c | 23 |
3 files changed, 16 insertions, 36 deletions
diff --git a/target/mips/helper.h b/target/mips/helper.h index 666936c81b..60efa01194 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -20,13 +20,6 @@ DEF_HELPER_4(scd, tl, env, tl, tl, int) #endif #endif -DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, tl, tl) -#ifdef TARGET_MIPS64 -DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl) -DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl) -#endif - DEF_HELPER_3(muls, tl, env, tl, tl) DEF_HELPER_3(mulsu, tl, env, tl, tl) DEF_HELPER_3(macc, tl, env, tl, tl) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 7af4c2f084..11d781fc91 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -103,28 +103,6 @@ HELPER_ST(sd, stq, uint64_t) #endif #undef HELPER_ST -target_ulong helper_clo (target_ulong arg1) -{ - return clo32(arg1); -} - -target_ulong helper_clz (target_ulong arg1) -{ - return clz32(arg1); -} - -#if defined(TARGET_MIPS64) -target_ulong helper_dclo (target_ulong arg1) -{ - return clo64(arg1); -} - -target_ulong helper_dclz (target_ulong arg1) -{ - return clz64(arg1); -} -#endif /* TARGET_MIPS64 */ - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 8deffa1c48..7f8ecf42c2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3626,29 +3626,38 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, /* Treat as NOP. */ return; } - t0 = tcg_temp_new(); + t0 = cpu_gpr[rd]; gen_load_gpr(t0, rs); + switch (opc) { case OPC_CLO: case R6_OPC_CLO: - gen_helper_clo(cpu_gpr[rd], t0); +#if defined(TARGET_MIPS64) + case OPC_DCLO: + case R6_OPC_DCLO: +#endif + tcg_gen_not_tl(t0, t0); break; + } + + switch (opc) { + case OPC_CLO: + case R6_OPC_CLO: case OPC_CLZ: case R6_OPC_CLZ: - gen_helper_clz(cpu_gpr[rd], t0); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS); + tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); break; #if defined(TARGET_MIPS64) case OPC_DCLO: case R6_OPC_DCLO: - gen_helper_dclo(cpu_gpr[rd], t0); - break; case OPC_DCLZ: case R6_OPC_DCLZ: - gen_helper_dclz(cpu_gpr[rd], t0); + tcg_gen_clzi_i64(t0, t0, 64); break; #endif } - tcg_temp_free(t0); } /* Godson integer instructions */ |