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| author | Richard Henderson <rth@twiddle.net> | 2015-02-18 11:45:54 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-02-14 08:14:59 +1100 |
| commit | 84775c43f390d4f5dd9adf8732e7e0b6deed8f61 (patch) | |
| tree | 56b0df7c4bfbcbafb342b4d3f7fb8c862ad2431e /target/openrisc/cpu.h | |
| parent | cf2ae4428f320f3d8027a50c1cd45f4b5a6c93bb (diff) | |
| download | qemu-84775c43f390d4f5dd9adf8732e7e0b6deed8f61.tar.gz | |
target/openrisc: Keep SR_F in a separate variable
This avoids having to keep merging and extracting the flag from SR.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ef90e49a4d..bb5d3636f1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,7 +286,8 @@ typedef struct CPUOpenRISCState { target_ulong epcr; /* Exception PC register */ target_ulong eear; /* Exception EA register */ - uint32_t sr; /* Supervisor register */ + target_ulong sr_f; /* the SR_F bit, values 0, 1. */ + uint32_t sr; /* Supervisor register, without SR_F */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ @@ -301,7 +302,6 @@ typedef struct CPUOpenRISCState { uint32_t flags; /* cpu_flags, we only use it for exception in solt so far. */ - uint32_t btaken; /* the SR_F bit */ /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -412,6 +412,17 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } +static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) +{ + return env->sr + env->sr_f * SR_F; +} + +static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) +{ + env->sr_f = (val & SR_F) != 0; + env->sr = (val & ~SR_F) | SR_FO; +} + #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 #endif /* OPENRISC_CPU_H */ |