diff options
| author | Sam Bobroff <sam.bobroff@au1.ibm.com> | 2017-03-02 16:38:56 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-03-03 11:30:59 +1100 |
| commit | ec975e839cbb6143be80cfc91b1df103fc7e4771 (patch) | |
| tree | cfe05d1e235e9548051341537833880b6c6fa6d8 /target/ppc/cpu-qom.h | |
| parent | bb998645284924db6da93e777af5f29ef2f3c0a8 (diff) | |
| download | qemu-ec975e839cbb6143be80cfc91b1df103fc7e4771.tar.gz | |
spapr: Small cleanup of PPC MMU enums
The PPC MMU types are sometimes treated as if they were a bit field
and sometime as if they were an enum which causes maintenance
problems: flipping bits in the MMU type (which is done on both the 1TB
segment and 64K segment bits) currently produces new MMU type
values that are not handled in every "switch" on it, sometimes causing
an abort().
This patch provides some macros that can be used to filter out the
"bit field-like" bits so that the remainder of the value can be
switched on, like an enum. This allows removal of all of the
"degraded" types from the list and should ease maintenance.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu-qom.h')
| -rw-r--r-- | target/ppc/cpu-qom.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index da7eb5a6d6..81500e5748 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -80,22 +80,22 @@ enum powerpc_mmu_t { POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ - POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* Architecture 2.07 "degraded" (no 1T segments) */ - POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000004, /* Architecture 3.00 variant */ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | POWERPC_MMU_V3 | 0x00000005, }; +#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) +#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) +#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) +#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) +#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) +#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) /*****************************************************************************/ /* Exception model */ |