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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-12-04 11:27:53 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-12-04 11:27:53 +0000 |
| commit | 495566ec38817e6625294e6909cffb4de040c8e7 (patch) | |
| tree | 729e7a3ef8a86ae3fbaddddad8afdb566350c6e0 /target/ppc/machine.c | |
| parent | c11d61271b9e6e7a1f0479ef1ca8fb55fa457a62 (diff) | |
| parent | 768a20f3a491ed4afce73ebb65347d55251c0ebd (diff) | |
| download | qemu-495566ec38817e6625294e6909cffb4de040c8e7.tar.gz | |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20171204' into staging
ppc patch queue 2017-12-04
We are, alas, not yet to the bottom of ppc bugs. This pull request
fixes several more. I believe they're important enough to include in
2.11. despite the late date.
# gpg: Signature made Mon 04 Dec 2017 03:40:56 GMT
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.11-20171204:
spapr: Include "pre-plugged" DIMMS in ram size calculation at reset
target-ppc: Don't invalidate non-supported msr bits
pseries: fix TCG migration
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/ppc/machine.c')
| -rw-r--r-- | target/ppc/machine.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 24117e8f31..e475206c6a 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -300,9 +300,9 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ + /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ msr = env->msr; - env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); hreg_compute_mem_idx(env); |