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authorNikunj A Dadhania <nikunj@linux.vnet.ibm.com>2017-02-27 10:27:55 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2017-03-01 11:23:39 +1100
commit6b10d008a0c779e1226d197dfb9ba796559c1381 (patch)
treeca7e90e48018827b3f4ac31aa90fa1f9a83ba58b /target/ppc/translate.c
parentdd09c36159858c66ab6e47c688e4177dd3912bf0 (diff)
downloadqemu-6b10d008a0c779e1226d197dfb9ba796559c1381.tar.gz
target/ppc: update ca32 in arithmetic add
Adds routine to compute ca32 - gen_op_arith_compute_ca32 For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA and CA32 will have same value. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate.c')
-rw-r--r--target/ppc/translate.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index be7378b9ce..eba83efbbd 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -816,6 +816,23 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
+static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
+ TCGv res, TCGv arg0, TCGv arg1,
+ int sub)
+{
+ TCGv t0;
+
+ if (!is_isa300(ctx)) {
+ return;
+ }
+
+ t0 = tcg_temp_new();
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ tcg_gen_xor_tl(t0, t0, res);
+ tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
+ tcg_temp_free(t0);
+}
+
/* Common add function */
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, bool add_ca, bool compute_ca,
@@ -842,6 +859,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
} else {
TCGv zero = tcg_const_tl(0);
if (add_ca) {
@@ -850,6 +870,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
} else {
tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
}
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
tcg_temp_free(zero);
}
} else {