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| author | Simon Guo <wei.guo.simon@gmail.com> | 2018-03-05 18:53:48 +0800 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-03-06 13:16:29 +1100 |
| commit | 21b786f607b11d888f90bbb8c3414500515d11e7 (patch) | |
| tree | e245e0c71a0b7f7c5bc1f0de6d5ba05034666f07 /target/ppc | |
| parent | 9d9769c2082bc0bdb88d0f138c5aae562b0c1826 (diff) | |
| download | qemu-21b786f607b11d888f90bbb8c3414500515d11e7.tar.gz | |
PowerPC: Add TS bits into msr_mask
During migration, after MSR bits is synced, cpu_post_load() will use
msr_mask to determine which PPC MSR bits will be applied into the target
side. Hardware Transaction Memory(HTM) has been supported since Power8,
but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM
from loading TM checkpointed values.
This patch adds TS bits into msr_mask for Power8, so that transactional
application can be migrated across qemu.
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/translate_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 17a87df654..391b94b97d 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8692,6 +8692,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | + (1ull << MSR_TS0) | + (1ull << MSR_TS1) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) |