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authorAurelien Jarno <aurelien@aurel32.net>2017-07-02 18:18:14 +0200
committerAurelien Jarno <aurelien@aurel32.net>2017-07-18 23:39:15 +0200
commit57f5c1b093e1c3ec185770d2a180259205f980be (patch)
tree900489d0e46111fb69f4b26820e7b702d6ebbf6d /target/sh4/op_helper.c
parent6887dc6700ccb7820d8a9d370f421ee361c748e8 (diff)
downloadqemu-57f5c1b093e1c3ec185770d2a180259205f980be.tar.gz
target/sh4: do not check for PR bit for fabs instruction
The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/sh4/op_helper.c')
-rw-r--r--target/sh4/op_helper.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 528a40ac1d..5e3a3ba68c 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -252,16 +252,6 @@ static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
}
}
-float32 helper_fabs_FT(float32 t0)
-{
- return float32_abs(t0);
-}
-
-float64 helper_fabs_DT(float64 t0)
-{
- return float64_abs(t0);
-}
-
float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);