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| author | Richard Henderson <rth@twiddle.net> | 2016-11-18 09:31:40 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:11 -0800 |
| commit | f69d277ece43c42c7ab0144c2ff05ba740f6706b (patch) | |
| tree | 630e59106af7a68dbb6f2587e5e286f6d9ff4b4c /tcg/aarch64 | |
| parent | 82790a870992bd87d5fd9e607f40859dcf4f82ac (diff) | |
| download | qemu-f69d277ece43c42c7ab0144c2ff05ba740f6706b.tar.gz | |
tcg: Transition flat op_defs array to a target callback
This will allow the target to tailor the constraints to the
auto-detected ISA extensions.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/aarch64')
| -rw-r--r-- | tcg/aarch64/tcg-target.inc.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c0e9890194..416db45b85 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1812,6 +1812,18 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { -1 }, }; +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + int i, n = ARRAY_SIZE(aarch64_op_defs); + + for (i = 0; i < n; ++i) { + if (aarch64_op_defs[i].op == op) { + return &aarch64_op_defs[i]; + } + } + return NULL; +} + static void tcg_target_init(TCGContext *s) { tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); @@ -1834,8 +1846,6 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */ - - tcg_add_target_add_op_defs(aarch64_op_defs); } /* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ |