diff options
| author | Richard Henderson <rth@twiddle.net> | 2016-10-14 19:51:45 -0500 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 07:59:11 -0800 |
| commit | ec903af18418e0870af84f6036d7aca1e6a5dc0a (patch) | |
| tree | bb4038929537dea8dee691a54cdefab85ea7bdac /tcg/arm | |
| parent | 40b2ccb156534f5d5f1d110a6ce008d87ee10af1 (diff) | |
| download | qemu-ec903af18418e0870af84f6036d7aca1e6a5dc0a.tar.gz | |
tcg/arm: Implement field extraction opcodes
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/arm')
| -rw-r--r-- | tcg/arm/tcg-target.h | 4 | ||||
| -rw-r--r-- | tcg/arm/tcg-target.inc.c | 24 |
2 files changed, 26 insertions, 2 deletions
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d1fe12b18f..4e307289d9 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -111,8 +111,8 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions +#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 1415c27172..2d5af0ff8b 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -713,6 +713,22 @@ static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, | (ofs << 7) | ((ofs + len - 1) << 16)); } +static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) +{ + /* ubfx */ + tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((len - 1) << 16)); +} + +static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) +{ + /* sbfx */ + tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((len - 1) << 16)); +} + /* Note that this routine is used for both LDR and LDRH formats, so we do not wish to include an immediate shift at this point. */ static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, @@ -1894,6 +1910,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_deposit(s, COND_AL, args[0], args[2], args[3], args[4], const_args[2]); break; + case INDEX_op_extract_i32: + tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); + break; + case INDEX_op_sextract_i32: + tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); + break; case INDEX_op_div_i32: tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); @@ -1976,6 +1998,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_ext16u_i32, { "r", "r" } }, { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_extract_i32, { "r", "r" } }, + { INDEX_op_sextract_i32, { "r", "r" } }, { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, |