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| author | Alex Bennée <alex.bennee@linaro.org> | 2017-02-23 18:29:27 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2017-02-24 10:32:46 +0000 |
| commit | ca759f9e387db87e1719911f019bc60c74be9ed8 (patch) | |
| tree | 5d328bd7b1c22749e282991182ddd1644e291fab /tcg/i386 | |
| parent | 4881658a4bf6dc5335e5033d0916b2e86687463d (diff) | |
| download | qemu-ca759f9e387db87e1719911f019bc60c74be9ed8.tar.gz | |
tcg: enable MTTCG by default for ARM on x86 hosts
This enables the multi-threaded system emulation by default for ARMv7
and ARMv8 guests using the x86_64 TCG backend. This is because on the
guest side:
- The ARM translate.c/translate-64.c have been converted to
- use MTTCG safe atomic primitives
- emit the appropriate barrier ops
- The ARM machine has been updated to
- hold the BQL when modifying shared cross-vCPU state
- defer powerctl changes to async safe work
All the host backends support the barrier and atomic primitives but
need to provide same-or-better support for normal load/store
operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Pranith Kumar <bobby.prani@gmail.com>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
Diffstat (limited to 'tcg/i386')
| -rw-r--r-- | tcg/i386/tcg-target.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..4275787db9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif |