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authorRichard Henderson <richard.henderson@linaro.org>2018-03-26 20:37:24 -0700
committerRichard Henderson <richard.henderson@linaro.org>2018-03-28 12:45:16 +0800
commitf2f1dde75160cac6ede330f3db50dc817d01a2d6 (patch)
tree933b2b35632e7a598eba1b9495f64a86f0801893 /tcg/tcg-gvec-desc.h
parentfa3704d87720d7049d483ff669b9e2ff991e7658 (diff)
downloadqemu-f2f1dde75160cac6ede330f3db50dc817d01a2d6.tar.gz
tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
Failure to do so results in the tcg optimizer sign-extending any constant fold from 32-bits. This turns out to be visible in the RISC-V testsuite using a host that emits these opcodes (e.g. any non-x86_64). Reported-by: Michael Clark <mjc@sifive.com> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg-gvec-desc.h')
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