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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-11-17 20:47:42 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-02-08 15:54:05 +0000 |
| commit | 212be173f01e85e6589fd76676827953a84a732b (patch) | |
| tree | fc93bba42036540e69854d3cec47a39db25bf431 /tcg/tcg-op-gvec.h | |
| parent | d0ec97967f940bbc11dced83422b39c224127f1e (diff) | |
| download | qemu-212be173f01e85e6589fd76676827953a84a732b.tar.gz | |
tcg: Add generic vector ops for comparisons
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg-op-gvec.h')
| -rw-r--r-- | tcg/tcg-op-gvec.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index b9f9eb7b84..60a17ee908 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -207,6 +207,10 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, + uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + /* * 64-bit vector operations. Use these when the register has been allocated * with tcg_global_mem_new_i64, and so we cannot also address it via pointer. |