diff options
| -rw-r--r-- | target/sparc/asi.h | 1 | ||||
| -rw-r--r-- | target/sparc/cpu.h | 1 | ||||
| -rw-r--r-- | target/sparc/ldst_helper.c | 24 |
3 files changed, 26 insertions, 0 deletions
diff --git a/target/sparc/asi.h b/target/sparc/asi.h index c9a1849600..d8d6284125 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -211,6 +211,7 @@ #define ASI_AFSR 0x4c /* Async fault status register */ #define ASI_AFAR 0x4d /* Async fault address register */ #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ +#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */ #define ASI_IMMU 0x50 /* Insn-MMU main register space */ #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 21fe0d1d3e..9307b9135a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -523,6 +523,7 @@ struct CPUSPARCState { uint32_t gl; // UA2005 /* UA 2005 hyperprivileged registers */ uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; + uint64_t scratch[8]; CPUTimer *hstick; // UA 2005 /* Interrupt vector registers */ uint64_t ivec_status; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 7a134b3c0d..2e6439a6d9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1351,6 +1351,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, } break; } + case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ + if (unlikely((addr >= 0x20) && (addr < 0x30))) { + /* Hyperprivileged access only */ + cpu_unassigned_access(cs, addr, false, false, 1, size); + } + /* fall through */ + case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ + { + unsigned int i = (addr >> 3) & 0x7; + ret = env->scratch[i]; + break; + } case ASI_DCACHE_DATA: /* D-cache data */ case ASI_DCACHE_TAG: /* D-cache tag access */ case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ @@ -1603,6 +1615,18 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case ASI_INTR_RECEIVE: /* Interrupt data receive */ env->ivec_status = val & 0x20; return; + case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ + if (unlikely((addr >= 0x20) && (addr < 0x30))) { + /* Hyperprivileged access only */ + cpu_unassigned_access(cs, addr, true, false, 1, size); + } + /* fall through */ + case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ + { + unsigned int i = (addr >> 3) & 0x7; + env->scratch[i] = val; + return; + } case ASI_DCACHE_DATA: /* D-cache data */ case ASI_DCACHE_TAG: /* D-cache tag access */ case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ |