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-rw-r--r--target-microblaze/cpu-qom.h2
-rw-r--r--target-microblaze/cpu.c5
-rw-r--r--target-microblaze/cpu.h14
-rw-r--r--target-microblaze/helper.c12
-rw-r--r--target-microblaze/translate.c13
5 files changed, 14 insertions, 32 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index 3e9c20668f..ec2b989a23 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -64,7 +64,7 @@ typedef struct MicroBlazeCPU {
static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
{
- return MICROBLAZE_CPU(container_of(env, MicroBlazeCPU, env));
+ return container_of(env, MicroBlazeCPU, env);
}
#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index a0fcdf4464..dce1c7ea67 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -33,11 +33,6 @@ static void mb_cpu_reset(CPUState *s)
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
CPUMBState *env = &cpu->env;
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
- log_cpu_state(env, 0);
- }
-
mcc->parent_reset(s);
memset(env, 0, offsetof(CPUMBState, breakpoints));
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 75ae5baf36..6c35475fd6 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -331,20 +331,6 @@ int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
-#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp)
-{
- if (newsp)
- env->regs[R_SP] = newsp;
- env->regs[3] = 0;
-}
-#endif
-
-static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
-{
- env->regs[21] = newtls;
-}
-
static inline int cpu_interrupts_enabled(CPUMBState *env)
{
return env->sregs[SR_MSR] & MSR_IE;
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 01d4bbfe92..c6c96d4488 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
"hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_EAR],
env->sregs[SR_ESR], env->iflags);
- log_cpu_state_mask(CPU_LOG_INT, env, 0);
+ log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
@@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
"bimm exception at pc=%x iflags=%x\n",
env->sregs[SR_PC], env->iflags);
env->regs[17] -= 4;
- log_cpu_state_mask(CPU_LOG_INT, env, 0);
+ log_cpu_state_mask(CPU_LOG_INT, cs, 0);
}
} else if (env->iflags & IMM_FLAG) {
D(qemu_log("IMM_FLAG set at exception\n"));
@@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x ear=%x iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
- log_cpu_state_mask(CPU_LOG_INT, env, 0);
+ log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->base_vectors + 0x20;
break;
@@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
sym);
- log_cpu_state(env, 0);
+ log_cpu_state(cs, 0);
}
}
#endif
@@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->regs[14] = env->sregs[SR_PC];
env->sregs[SR_PC] = cpu->base_vectors + 0x10;
- //log_cpu_state_mask(CPU_LOG_INT, env, 0);
+ //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
case EXCP_BREAK:
@@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"break at pc=%x msr=%x %x iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
- log_cpu_state_mask(CPU_LOG_INT, env, 0);
+ log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
env->sregs[SR_MSR] |= MSR_BIP;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 54f439fc20..eba255b7c6 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1737,10 +1737,11 @@ static void check_breakpoint(CPUMBState *env, DisasContext *dc)
}
/* generate intermediate code for basic block 'tb'. */
-static void
-gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
- int search_pc)
+static inline void
+gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
+ bool search_pc)
{
+ CPUMBState *env = &cpu->env;
uint16_t *gen_opc_end;
uint32_t pc_start;
int j, lj;
@@ -1776,7 +1777,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
#if !SIM_COMPAT
qemu_log("--------------\n");
- log_cpu_state(env, 0);
+ log_cpu_state(CPU(cpu), 0);
#endif
}
@@ -1941,12 +1942,12 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 0);
+ gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
}
void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 1);
+ gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
}
void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-25 07:44:34 +0000