diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/excp_helper.c | 9 | ||||
| -rw-r--r-- | target-ppc/translate.c | 2 |
2 files changed, 6 insertions, 5 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 882d529dbe..04ed4da1f4 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* XXX: this is false */ /* Get rS/rD and rA from faulting opcode */ - /* Broken for LE mode */ - env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip) - & 0x03FF0000) >> 16; + /* Note: the opcode fields will not be set properly for a direct + * store load/store, but nobody cares as nobody actually uses + * direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index bebd1cc490..6bb0ba97ac 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2417,7 +2417,7 @@ static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) tcg_gen_andi_tl(t0, EA, mask); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 = tcg_const_i32(0); + t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); gen_update_nip(ctx, ctx->nip - 4); gen_helper_raise_exception_err(cpu_env, t1, t2); tcg_temp_free_i32(t1); |