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path: root/target-arm/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2014-12-22target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler1-0/+4
2014-12-22target-arm: Add ARMCPU secure propertyGreg Bellows1-0/+23
2014-12-22target-arm: Add feature unset functionGreg Bellows1-0/+5
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-1/+1
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-2/+6
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell1-10/+39
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell1-2/+2
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-3/+7
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring1-1/+1
2014-10-24target-arm: add powered off cpu stateRob Herring1-1/+7
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell1-0/+1
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-11/+36
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias1-5/+2
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell1-5/+0
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell1-0/+1
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson1-0/+34
2014-09-12target-arm: Implement handling of fired watchpointsPeter Maydell1-0/+1
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell1-0/+2
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan1-1/+1
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan1-10/+22
2014-08-19arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite1-2/+2
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell1-0/+3
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias1-1/+1
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar1-0/+1
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell1-2/+1
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell1-4/+4
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell1-2/+0
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-0/+1
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel1-0/+2
2014-05-27target-arm: Fix segfault on startup when KVM enabledChristoffer Dall1-1/+1
2014-05-13kvm: reset state from the CPU's reset methodPaolo Bonzini1-0/+7
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell1-1/+1
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-2/+6
2014-04-17target-arm: Implement RVBAR registerPeter Maydell1-0/+9
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell1-0/+1
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring1-1/+1
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell1-0/+7
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-0/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-1/+3
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-0/+7
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+1
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-4/+4
2014-02-26target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell1-2/+2
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell1-0/+2
2014-02-26target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell1-1/+1
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell1-4/+2
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell1-1/+1
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