summaryrefslogtreecommitdiff
path: root/target-arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias1-1/+1
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias1-1/+1
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias1-1/+1
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler1-0/+16
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-0/+1
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel1-0/+2
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini1-22/+0
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias1-1/+1
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias1-1/+1
2014-05-27target-arm: Add a feature flag for EL3Edgar E. Iglesias1-0/+1
2014-05-27target-arm: Add a feature flag for EL2Edgar E. Iglesias1-0/+1
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias1-1/+3
2014-05-27target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias1-1/+1
2014-05-27target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias1-1/+1
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias1-1/+1
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias1-1/+1
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias1-1/+1
2014-05-27target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias1-4/+4
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-0/+1
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell1-2/+1
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell1-1/+1
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell1-0/+1
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell1-1/+1
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell1-0/+2
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell1-0/+2
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring1-4/+3
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell1-0/+2
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-1/+2
2014-04-17target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell1-1/+9
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell1-0/+9
2014-04-17target-arm: Define exception record for AArch64 exceptionsPeter Maydell1-0/+15
2014-04-17target-arm: Implement AArch64 DAIF system registerPeter Maydell1-1/+1
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-20/+0
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-3/+2
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-6/+0
2014-03-10target-arm: Implements the ARM PMCCNTR registerAlistair Francis1-0/+4
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+1
2014-02-26target-arm: Add utility function for checking AA32/64 state of an ELPeter Maydell1-0/+16
2014-02-26target-arm: Implement AArch64 view of CPACRPeter Maydell1-1/+1
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-3/+9
2014-02-26target-arm: Get MMU index information correct for A64 codePeter Maydell1-3/+8
2014-02-26target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell1-0/+4
2014-02-26target-arm: Implement AArch64 generic timersPeter Maydell1-3/+3
2014-02-26target-arm: Implement AArch64 TTBR*Peter Maydell1-4/+2
2014-02-26target-arm: Implement AArch64 VBAR_EL1Peter Maydell1-1/+1
2014-02-26target-arm: Implement AArch64 TCR_EL1Peter Maydell1-1/+1
2014-02-26target-arm: Implement AArch64 SCTLR_EL1Peter Maydell1-1/+1
2014-02-26target-arm: Implement AArch64 memory attribute registersPeter Maydell1-0/+3
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell1-1/+2
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell1-1/+1
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-15 20:06:08 +0000