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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2013-07-27misc: Use g_assert_not_reached for code which is expected to be unreachableStefan Weil1-1/+1
2013-07-23gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber1-3/+4
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber1-3/+5
2013-07-15target-arm: Avoid g_hash_table_get_keys()Peter Maydell1-2/+10
2013-07-15target-arm: avoid undefined behaviour when writing TTBCRPeter Maydell1-2/+4
2013-07-15target-arm/helper.c: Allow const opaques in arm CPPeter Crosthwaite1-1/+3
2013-07-15target-arm/helper.c: Implement MIDR aliasesPeter Crosthwaite1-5/+11
2013-07-15target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanupPeter Crosthwaite1-9/+4
2013-06-25target-arm: Convert TCG to using (index,value) list for cp migrationPeter Maydell1-0/+174
2013-06-25target-arm: mark up cpregs for no-migrate or raw accessPeter Maydell1-46/+94
2013-06-25target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfoPeter Maydell1-0/+13
2013-03-12target-arm: Override do_interrupt for ARMv7-M profileAndreas Färber1-5/+5
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-4/+7
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-1/+1
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-1/+3
2013-03-05ARM: KVM: Add support for KVM on ARM architectureChristoffer Dall1-1/+1
2013-03-05target-arm: Drop CPUARMState* argument from bank_number()Peter Maydell1-7/+6
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson1-5/+0
2013-02-16target-arm: Move TCG initialization to ARMCPU initfnAndreas Färber1-6/+0
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber1-4/+10
2013-01-30target-arm: Rename CPU typesAndreas Färber1-3/+8
2013-01-27target-arm: Detect attempt to instantiate non-CPU type in cpu_init()Andreas Färber1-2/+4
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber1-1/+2
2013-01-11target-arm: Fix SWI (SVC) instruction in M profile.Alex_Rozenman@mentor.com1-1/+1
2012-12-23Merge branch 'master' of git://git.qemu.org/qemu into qom-cpuAndreas Färber1-4/+4
2012-12-19cpu: Introduce CPUListState structAndreas Färber1-7/+2
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-2/+2
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell1-5/+0
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity1-14/+14
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl1-4/+5
2012-09-10target-arm: Fix potential buffer overflowStefan Weil1-2/+2
2012-08-10target-arm: Fix typos in commentsPeter Maydell1-3/+3
2012-07-12target-arm: Add support for long format translation table walksPeter Maydell1-0/+182
2012-07-12target-arm: Implement TTBCR changes for LPAEPeter Maydell1-1/+14
2012-07-12target-arm: Implement long-descriptor PAR formatPeter Maydell1-10/+69
2012-07-12target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell1-14/+15
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell1-1/+76
2012-07-12target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell1-0/+5
2012-07-12target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell1-0/+16
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell1-12/+20
2012-07-12target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell1-3/+3
2012-07-12target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell1-1/+1
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell1-39/+0
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell1-0/+13
2012-06-20target-arm: Convert final ID registersPeter Maydell1-48/+68
2012-06-20target-arm: Convert MPIDRPeter Maydell1-22/+28
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell1-28/+33
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell1-8/+54
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