index
:
peter/qemu
bdrv-getlength-conversion
block
block-dmg
block-dmg-2.2
block-dmg-2.3
block-dmg-2.3-v2
doc-updates
gdbstub-fixes
gtk-toggle-menubar
gtk-updates
logitech-unifying
logitech-unifying-2.2
master
serial-baud
slirp-fixes
usbdump-usbhid
QEMU hacking for Peter
Peter Wu
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
helper.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-17
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
Peter Maydell
1
-7
/
+121
2015-11-24
target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
Peter Maydell
1
-1
/
+11
2015-11-03
target-arm: Add and use symbolic names for register banks
Soren Brinkmann
1
-15
/
+22
2015-10-27
target-arm: Add support for S1 + S2 MMU translations
Edgar E. Iglesias
1
-7
/
+31
2015-10-27
target-arm: Add S2 translation to 32bit S1 PTWs
Edgar E. Iglesias
1
-5
/
+17
2015-10-27
target-arm: Add S2 translation to 64bit S1 PTWs
Edgar E. Iglesias
1
-2
/
+48
2015-10-27
target-arm: Add ARMMMUFaultInfo
Edgar E. Iglesias
1
-12
/
+20
2015-10-27
target-arm: Avoid inline for get_phys_addr
Edgar E. Iglesias
1
-8
/
+8
2015-10-27
target-arm: Add support for S2 page-table protection bits
Edgar E. Iglesias
1
-4
/
+37
2015-10-27
target-arm: Add computation of starting level for S2 PTW
Edgar E. Iglesias
1
-13
/
+101
2015-10-27
target-arm: lpae: Rename granule_sz to stride
Edgar E. Iglesias
1
-15
/
+15
2015-10-27
target-arm: lpae: Replace tsz with computed inputsize
Edgar E. Iglesias
1
-11
/
+11
2015-10-27
target-arm: Add support for AArch32 S2 negative t0sz
Edgar E. Iglesias
1
-1
/
+17
2015-10-27
target-arm: lpae: Move declaration of t0sz and t1sz
Edgar E. Iglesias
1
-2
/
+3
2015-10-27
target-arm: lpae: Make t0sz and t1sz signed integers
Edgar E. Iglesias
1
-2
/
+2
2015-10-27
target-arm: Add HPFAR_EL2
Edgar E. Iglesias
1
-0
/
+12
2015-10-27
target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)
Soren Brinkmann
1
-0
/
+16
2015-10-16
target-arm: Add MDCR_EL2
Sergey Fedorov
1
-0
/
+12
2015-10-16
target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
Davorin Mista
1
-2
/
+23
2015-10-16
target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
Sergey Sorokin
1
-2
/
+13
2015-10-16
target-arm: Break the TB after ISB to execute self-modified code correctly
Sergey Sorokin
1
-1
/
+5
2015-10-16
target-arm: Add missing 'static' attribute
Stefan Weil
1
-1
/
+1
2015-09-25
arm: clarify the use of muldiv64()
Laurent Vivier
1
-6
/
+8
2015-09-15
target-arm: Use new revbit functions
Richard Henderson
1
-11
/
+1
2015-09-14
target-arm: Add VMPIDR_EL2
Edgar E. Iglesias
1
-2
/
+24
2015-09-14
target-arm: Break out mpidr_read_val()
Edgar E. Iglesias
1
-1
/
+6
2015-09-14
target-arm: Add VPIDR_EL2
Edgar E. Iglesias
1
-1
/
+41
2015-09-14
target-arm: Suppress EPD for S2, EL2 and EL3 translations
Edgar E. Iglesias
1
-2
/
+4
2015-09-14
target-arm: Suppress TBI for S2 translations
Edgar E. Iglesias
1
-1
/
+3
2015-09-14
target-arm: Add VTTBR_EL2
Edgar E. Iglesias
1
-2
/
+32
2015-09-14
target-arm: Add VTCR_EL2
Edgar E. Iglesias
1
-2
/
+41
2015-09-11
tlb: Add "ifetch" argument to cpu_mmu_index()
Benjamin Herrenschmidt
1
-2
/
+2
2015-09-11
maint: remove / fix many doubled words
Daniel P. Berrange
1
-1
/
+1
2015-09-08
target-arm: Add AArch64 access to PAR_EL1
Edgar E. Iglesias
1
-0
/
+6
2015-09-08
target-arm: Correct opc1 for AT_S12Exx
Edgar E. Iglesias
1
-4
/
+4
2015-09-07
target-arm: Fix AArch32:AArch64 general-purpose register mapping
Sergey Sorokin
1
-32
/
+32
2015-09-07
arm: Remove hw_error() usages.
Peter Crosthwaite
1
-1
/
+1
2015-09-07
target-arm: Improve semihosting debug prints
Christopher Covington
1
-3
/
+9
2015-08-25
target-arm: Implement AArch64 TLBI operations on IPAs
Peter Maydell
1
-0
/
+55
2015-08-25
target-arm: Implement missing EL3 TLB invalidate operations
Peter Maydell
1
-0
/
+76
2015-08-25
target-arm: Implement missing EL2 TLBI operations
Peter Maydell
1
-0
/
+22
2015-08-25
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
Peter Maydell
1
-43
/
+129
2015-08-25
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
Peter Maydell
1
-8
/
+8
2015-08-25
target-arm: Implement AArch32 ATS1H* operations
Peter Maydell
1
-0
/
+22
2015-08-25
target-arm: Enable the AArch32 ATS12NSO ops
Peter Maydell
1
-5
/
+11
2015-08-25
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
Peter Maydell
1
-2
/
+41
2015-08-25
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
Peter Maydell
1
-0
/
+5
2015-08-25
target-arm: Implement missing ACTLR registers
Peter Maydell
1
-6
/
+15
2015-08-25
target-arm: Implement missing AFSR registers
Peter Maydell
1
-0
/
+24
2015-08-25
target-arm: Implement missing AMAIR registers
Peter Maydell
1
-0
/
+21
[next]