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path: root/target-arm/translate.c
AgeCommit message (Expand)AuthorFilesLines
2014-06-25arm: translate.c: Fix smlald InstructionPeter Crosthwaite1-11/+23
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-3/+0
2013-09-10target-arm: Add AArch64 translation stubAlexander Graf1-3/+11
2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf1-9/+29
2013-09-10target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell1-13/+13
2013-09-10target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf1-4/+5
2013-09-10target-arm: Export cpu_envAlexander Graf1-1/+1
2013-09-10target-arm: Extract the disas struct to a header fileAlexander Graf1-23/+1
2013-09-10target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell1-124/+210
2013-09-10target-arm: Use sextract32() in branch decodePeter Maydell1-2/+3
2013-09-03Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori1-0/+4
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-09-01target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil1-0/+4
2013-08-20target-arm: Support coprocessor registers which do I/OPeter Maydell1-3/+13
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-15target-arm: explicitly decode SEVL instructionMans Rullgard1-1/+2
2013-07-15target-arm: implement LDA/STL instructionsMans Rullgard1-10/+119
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard1-0/+1
2013-07-09target-arm: Change gen_intermediate_code_internal() argument to ARMCPUAndreas Färber1-4/+5
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-2/+4
2013-06-14Merge remote-tracking branch 'pmaydell/target-arm.next' into stagingAnthony Liguori1-1/+1
2013-06-03Fix rfe instructionPeter Chubb1-1/+1
2013-06-01Remove unnecessary break statementsStefan Weil1-1/+0
2013-05-26target-arm: Remove gen_{ld,st}* definitionsPeter Maydell1-46/+0
2013-05-26target-arm: Remove gen_{ld,st}* from thumb2 decoderPeter Maydell1-10/+20
2013-05-26target-arm: Remove gen_{ld,st}* from Thumb insnsPeter Maydell1-25/+46
2013-05-26target-arm: Remove gen_{ld,st}* from basic ARM insnsPeter Maydell1-32/+69
2013-05-26target-arm: Remove use of gen_{ld,st}* from ldrex/strexPeter Maydell1-13/+18
2013-05-26target-arm: Remove uses of gen_{ld,st}* from Neon codePeter Maydell1-18/+28
2013-05-26target-arm: Remove uses of gen_{ld,st}* from iWMMXt codePeter Maydell1-8/+10
2013-05-26target-arm: Remove gen_ld64() and gen_st64()Peter Maydell1-15/+4
2013-05-26target-arm: Don't use TCGv when we mean TCGv_i32Peter Maydell1-224/+229
2013-04-19target-arm: Reinsert missing return statement in ARM mode SRS decodePeter Chubb1-0/+1
2013-03-05target-arm: Don't decode RFE or SRS on M profile coresPeter Maydell1-2/+3
2013-03-05target-arm: Factor out handling of SRS instructionPeter Maydell1-67/+69
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-25target-arm: Fix sbc_CC carryRichard Henderson1-24/+4
2013-02-25arm/translate.c: Fix adc_CC/sbc_CC implementationPeter Crosthwaite1-2/+2
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson1-8/+39
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson1-5/+34
2013-02-23target-arm: Use add2 in gen_add_CCRichard Henderson1-4/+3
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson1-12/+14
2013-02-23target-arm: Use mul[us]2 in gen_mul[us]_i64_i32Richard Henderson1-16/+22
2013-01-30target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writesPeter Maydell1-1/+4
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
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