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path: root/target-arm/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-11-19target-arm: Update condexec before arch BP check in AA32 translationSergey Fedorov1-0/+1
2015-11-19target-arm: Update condexec before CP access check in AA32 translationSergey Fedorov1-0/+1
2015-11-12target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov1-0/+1
2015-11-10target-arm: Clean up DISAS_UPDATE usage in AArch32 translation codeSergey Fedorov1-11/+14
2015-11-03target-arm: Report S/NS status in the CPU debug logsPeter Maydell1-1/+11
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-2/+5
2015-10-27target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell1-1/+44
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov1-5/+14
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-2/+15
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-45/+9
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-4/+5
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+5
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson1-1/+2
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-15/+16
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-3/+4
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+1
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson1-0/+9
2015-09-14target-arm: Introduce DisasCompareRichard Henderson1-46/+69
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson1-5/+5
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange1-1/+1
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin1-1/+5
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-23/+23
2015-07-06target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell1-0/+7
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-06-15target-arm: Correct "preferred return address" for cpreg access exceptionsPeter Maydell1-1/+1
2015-06-15target-arm: Add the THUMB_DSP featureAurelio C. Remonda1-10/+102
2015-05-29target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strdPeter Maydell1-24/+32
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell1-0/+4
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows1-10/+7
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-23/+42
2015-03-16target-arm: Fix handling of STM (user) with r15 in register listPeter Maydell1-6/+12
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-4/+4
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-6/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+0
2015-02-05target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell1-2/+24
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell1-2/+3
2015-02-05target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov1-0/+4
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini1-2/+2
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell1-5/+9
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov1-0/+1
2014-11-04target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell1-6/+5
2014-11-04target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell1-44/+50
2014-11-04target-arm/translate.c: Don't use IS_M()Peter Maydell1-8/+11
2014-11-04target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell1-60/+80
2014-11-04target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell1-8/+8
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-2/+2
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell1-0/+3
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell1-11/+92
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