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path: root/target-mips/helper.h
AgeCommit message (Expand)AuthorFilesLines
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-0/+1
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim1-0/+3
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim1-0/+17
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim1-0/+12
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim1-0/+42
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim1-0/+10
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim1-0/+64
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim1-0/+13
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim1-0/+13
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim1-0/+10
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+2
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-0/+5
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim1-0/+27
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae1-0/+20
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim1-0/+5
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-6/+0
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic1-1/+1
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-0/+1
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-0/+1
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-6/+6
2013-02-23target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson1-2/+0
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno1-13/+0
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno1-4/+0
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno1-4/+4
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu1-0/+35
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu1-0/+52
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu1-0/+7
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu1-0/+91
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu1-0/+38
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu1-0/+126
2012-10-28target-mips: rename helper flagsAurelien Jarno1-53/+53
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson1-0/+59
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl1-202/+208
2012-03-24target-mips: Add compiler attribute to some functions which don't returnStefan Weil1-2/+2
2011-09-06mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias1-0/+10
2010-12-22target-mips: fix translation of MT instructionsNathan Froyd1-4/+4
2010-07-25mips: more fixes to the MIPS interrupt glue logicAurelien Jarno1-1/+0
2010-06-09target-mips: microMIPS ASE supportNathan Froyd1-0/+9
2009-11-30target-mips: use physical address in lladdrAurelien Jarno1-0/+9
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno1-0/+1
2009-04-06target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpersaurel321-4/+4
2009-03-08target-mips: rename helpers from do_ to helper_aurel321-5/+0
2008-11-17TCG variable type checking.pbrook1-197/+203
2008-11-11target-mips: convert bit shuffle ops to TCGaurel321-7/+0
2008-11-11target-mips: convert bitfield ops to TCGaurel321-5/+1
2008-11-11target-mips: fix mft* helpers/callaurel321-5/+5
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths1-2/+4
2008-07-09Use temporary registers for the MIPS FPU emulation.ths1-44/+62
2008-06-29Remove unnecessary helper arguments, and fix some typos.ths1-5/+5
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