summaryrefslogtreecommitdiff
path: root/target-mips/op_helper.c
AgeCommit message (Expand)AuthorFilesLines
2016-09-16tcg: Merge GETPC and GETRARichard Henderson1-9/+9
2016-07-12Fix confusing argument names in some common functionsSergey Sorokin1-5/+5
2016-07-12target-mips: change ASID type to hold more than 8 bitsPaul Burton1-4/+4
2016-07-12target-mips: add ASID mask field and replace magic valuesPaul Burton1-12/+15
2016-06-24target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic1-11/+3
2016-06-24target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>Aleksandar Markovic1-20/+349
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic1-5/+12
2016-06-20coccinelle: Remove unnecessary variables for function return valueEduardo Habkost1-3/+1
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-18Fix some typos found by codespellStefan Weil1-1/+1
2016-04-28target-mips: Fix RDHWR exception host PCJames Hogan1-8/+8
2016-03-30target-mips: add MAAR, MAARI registerYongbok Kim1-0/+45
2016-03-30target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae1-1/+39
2016-02-26target-mips: implement R6 multi-threadingYongbok Kim1-0/+48
2016-01-23mips: Clean up includesPeter Maydell1-1/+1
2016-01-23target-mips: silence NaNs for cvt.s.d and cvt.d.sAurelien Jarno1-0/+2
2015-11-24target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae1-13/+0
2015-10-30target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim1-29/+35
2015-09-18target-mips: improve exception handlingPavel Dovgaluk1-113/+141
2015-09-18target-mips: Fix RDHWR on CP0.CountAlex Smith1-2/+7
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-2/+2
2015-08-13target-mips: Use CPU_LOG_INT for logging related to interruptsRichard Henderson1-1/+2
2015-07-28target-mips: fix offset calculation for InterruptsYongbok Kim1-2/+0
2015-07-15target-mips: correct DERET instructionLeon Alrae1-2/+1
2015-07-15target-mips: fix ASID synchronisation for MIPS MTAurelien Jarno1-1/+1
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-7/+12
2015-06-12target-mips: support Page Frame Number Extension fieldLeon Alrae1-6/+26
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-4/+4
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-1/+11
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim1-66/+77
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-0/+34
2015-02-13target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae1-3/+7
2015-01-20target-mips: Don't use _raw load/store accessorsPeter Maydell1-2/+2
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-12/+0
2014-12-16target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki1-1/+2
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-0/+8
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki1-84/+7
2014-12-16target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki1-2/+4
2014-12-16target-mips: Restore the order of helpersMaciej W. Rozycki1-159/+160
2014-12-16target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki1-2/+0
2014-12-16target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki1-1/+1
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim1-4/+80
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim1-2/+2
2014-11-03target-mips: add MSA defines and data structureYongbok Kim1-0/+1
2014-11-03target-mips: add restrictions for possible values in registersLeon Alrae1-17/+53
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae1-2/+15
2014-11-03target-mips: add TLBINV supportLeon Alrae1-7/+58
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-3/+22
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae1-0/+8
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae1-6/+6
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-01 10:19:00 +0000