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path: root/target-mips/translate.c
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2015-06-26target-mips: microMIPS32 R6 POOL16{A, C} instructionsYongbok Kim1-15/+118
2015-06-26target-mips: microMIPS32 R6 Major instructionsYongbok Kim1-17/+45
2015-06-26target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim1-6/+21
2015-06-26target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim1-32/+199
2015-06-26target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim1-10/+72
2015-06-26target-mips: microMIPS32 R6 branches and jumpsYongbok Kim1-40/+202
2015-06-26target-mips: add microMIPS32 R6 opcode enumYongbok Kim1-16/+103
2015-06-26target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim1-0/+68
2015-06-26target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim1-33/+45
2015-06-26target-mips: rearrange gen_compute_compact_branchYongbok Kim1-236/+236
2015-06-26target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim1-67/+99
2015-06-26target-mips: remove an unused argumentYongbok Kim1-3/+2
2015-06-26target-mips: add microMIPS TLBINV, TLBINVFYongbok Kim1-0/+8
2015-06-26target-mips: fix {RD, WR}PGPR in microMIPSYongbok Kim1-2/+2
2015-06-26target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae1-20/+55
2015-06-26target-mips: remove identical code in different branchLeon Alrae1-21/+4
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae1-0/+226
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-1/+2
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-21/+42
2015-06-12target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae1-6/+6
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-5/+15
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim1-10/+17
2015-06-11target-mips: Misaligned memory accesses for R6Yongbok Kim1-12/+27
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-150/+158
2015-06-11target-mips: move group of functions above gen_load_fpr32()Leon Alrae1-60/+58
2015-03-18target-mips: save cpu state before calling MSA load and store helpersLeon Alrae1-0/+2
2015-03-18target-mips: fix hflags modified in delay / forbidden slotLeon Alrae1-4/+15
2015-03-18target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae1-0/+1
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-47/+47
2015-02-13target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae1-1/+1
2015-02-13target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae1-2/+2
2015-02-13target-mips: fix detection of the end of the page during translationLeon Alrae1-1/+4
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-5/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-02-10target-mips: Clean up switch fall through after commit fecd264Markus Armbruster1-0/+4
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini1-10/+14
2014-12-16target-mips: convert single case switch into if statementLeon Alrae1-3/+1
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+2
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-5/+14
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-9/+98
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-2/+6
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki1-0/+4
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki1-3/+3
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki1-1/+2
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki1-5/+8
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki1-1/+1
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim1-5/+3
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