summaryrefslogtreecommitdiff
path: root/target-mips/translate_init.c
AgeCommit message (Expand)AuthorFilesLines
2009-12-17target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil1-3/+3
2009-12-16target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil1-3/+3
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd1-8/+0
2009-12-13target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd1-9/+18
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno1-0/+32
2009-11-14mips: fix cpu_reset memory leakBlue Swirl1-50/+0
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-10/+10
2009-10-01Get rid of _t suffixmalc1-10/+10
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
2009-03-08target-mips: rename helpers from do_ to helper_aurel321-4/+4
2009-01-14target-mips: fix indentationaurel321-42/+42
2009-01-12target-mips: get rid of tests on env->user_mode_onlyaurel321-10/+10
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-2/+2
2008-09-18Move the active FPU registers into env again, and use more TCG registersths1-3/+6
2008-09-14target-mips: fix warningaurel321-1/+1
2008-09-02Build fix for gcc-3.3.ths1-0/+4
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths1-15/+12
2008-07-21A bunch of minor code improvements in the MIPS target.ths1-1/+1
2008-07-20Fix compiler warning, by Stefan Weil.ths1-1/+1
2008-06-27More efficient target register / TC accesses.ths1-2/+0
2008-05-28Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths1-0/+1
2008-05-06Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver.ths1-0/+2
2008-05-06Use TCG for MIPS GPR moves.ths1-0/+2
2007-12-28Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths1-3/+3
2007-12-25Support for VR5432, and some of its special instructions. Original patchths1-0/+16
2007-12-255K and 20K are Release 1 CPUs.ths1-3/+3
2007-12-25Improved PABITS handling, and config register fixes.ths1-50/+99
2007-12-24Fix CCRes value for 20Kc.ths1-1/+1
2007-11-19Add older 4Km variants.ths1-0/+34
2007-11-18Use a valid PRid.ths1-1/+1
2007-11-14Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths1-2/+19
2007-11-10added cpu_model parameter to cpu_init()bellard1-22/+11
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths1-2/+2
2007-10-29Preliminary MIPS64R2 mode.ths1-0/+21
2007-10-23Use the standard ASE check for MIPS-3D and MT.ths1-1/+1
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths1-2/+2
2007-09-29Supervisor mode implementation, by Aurelien Jarno.ths1-3/+3
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-1/+13
2007-09-23Fix mips usermode emulation.ths1-0/+3
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-53/+158
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths1-7/+9
2007-07-29Fix MIPS cache configuration, by Aurelien Jarno.ths1-11/+19
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-0/+14
2007-06-22Allow emulation of 32bit targets in the MIPS64 capable qemu version.ths1-2/+1
2007-06-12Change 20Kc PRID to a later version.ths1-1/+3
2007-06-09R5k has PX implemented.ths1-2/+2
2007-06-01Update some comments, 64bit FPU support is functional regardless ofths1-4/+7
2007-06-01Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.ths1-2/+50
2007-06-01Allow again FPU for usermode emulation.ths1-1/+6