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2007-05-23The 24k wants more watch and srsmap registers.ths4-261/+45
2007-05-23The previous patch to make breakpoints work was a performanceths2-32/+7
2007-05-20Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.ths2-10/+31
2007-05-20Fix indexed FP load/store instructions.ths3-41/+31
2007-05-19More MIPS 64-bit FPU support.ths4-103/+369
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths2-8/+8
2007-05-19Fix ldl/ldr implementation, by Aurelien Jarno.ths1-0/+2
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths5-638/+795
2007-05-18Work around the lack of proper handling for self-modifying code.ths2-2/+30
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths3-18/+2
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths3-7/+53
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths2-120/+72
2007-05-13Delete misleading comment.ths1-2/+0
2007-05-13Don't decode CP0 XContext on 32bit MIPS.ths1-4/+8
2007-05-13MMU code improvements, by Aurelien Jarno.ths3-18/+24
2007-05-13MIPS linux-user update.ths1-0/+1
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths8-114/+149
2007-05-11Implemented cabs FP instructions, and improve exception handling forths2-40/+180
2007-05-11Another bit of nicer debug output.ths1-1/+1
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths2-12/+140
2007-05-11Improved debug output for the MIPS opcode decoder.ths1-85/+77
2007-05-11Fix missing status ro mask initialization, thanks Stefan Weil.ths1-0/+1
2007-05-10Fix for the scd instruction, by Aurelien Jarno.ths1-0/+1
2007-05-09Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.ths1-5/+57
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths2-2/+18
2007-05-08Work around gcc's mips define, spotted by Stefan Weil.ths1-12/+12
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths9-518/+1700
2007-05-07Update TODO.ths1-4/+3
2007-05-07Clear BD slot on next exception if appropriate.ths1-0/+4
2007-05-05Fix a really stupid bug in the [ls]d[lr] emulation, by Herve Poussineau.ths1-3/+3
2007-04-29Kill broken host register definitions, thanks to Paul Brook and Herveths2-13/+4
2007-04-29Revert last checkin.ths1-1/+1
2007-04-29Hopefully the final fix for LUI sign extensions.ths1-1/+1
2007-04-28Update TODO.ths1-0/+9
2007-04-25Next attempt to get the lui sign extension right.ths2-3/+2
2007-04-25Fix lui sign extension.ths1-1/+1
2007-04-19Update comment. We can't easily adhere to the architecture spec becauseths1-3/+3
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths6-26/+25
2007-04-16Simplify branch likely handling.ths1-6/+8
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths2-6/+6
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths3-13/+28
2007-04-15Small code generation optimization.ths1-3/+6
2007-04-15Delete unused define.ths1-2/+0
2007-04-14Restart interrupts after an exception.ths2-9/+33
2007-04-13Nicer Log formatting.ths1-1/+1
2007-04-13Another fix for CP0 Cause register handling.ths2-2/+2
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths2-3/+16
2007-04-11Throw RI for invalid MFMC0-class instructions. Introduce optionalths2-3/+18
2007-04-11Code formatting fix.ths1-935/+938
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths2-10/+10
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