summaryrefslogtreecommitdiff
path: root/target-ppc/excp_helper.c
AgeCommit message (Expand)AuthorFilesLines
2016-11-15FU exceptions should carry a cause (IC)Balbir Singh1-0/+3
2016-10-28ppc: allow certain HV interrupts to be delivered to guestsNicholas Piggin1-6/+26
2016-10-28ppc: fix MSR_ME handling for system reset interruptNicholas Piggin1-2/+2
2016-09-23target-ppc: add flag in check_tlb_flush()Nikunj A Dadhania1-2/+2
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt1-4/+5
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt1-2/+4
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt1-92/+54
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt1-0/+8
2016-09-07ppc: FP exceptions are always preciseBenjamin Herrenschmidt1-5/+6
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt1-17/+34
2016-07-01ppc: Initial HDEC supportBenjamin Herrenschmidt1-10/+12
2016-07-01ppc: Fix conditions for delivering external interrupts to a guestBenjamin Herrenschmidt1-11/+8
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-0/+59
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt1-0/+19
2016-06-23ppc: fix exception model for HV modeBenjamin Herrenschmidt1-89/+45
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt1-31/+20
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt1-2/+6
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt1-0/+8
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt1-11/+0
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater1-2/+47
2016-01-29ppc: Clean up includesPeter Maydell1-0/+1
2015-12-17ppc: cleanup loggingPaolo Bonzini1-0/+1
2015-12-17qemu-log: introduce qemu_log_separatePaolo Bonzini1-4/+3
2015-09-20target-ppc: Fix SRR0 when taking unaligned exceptionsAnton Blanchard1-1/+1
2014-09-25target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson1-2/+17
2014-08-25spapr: Add support for new NMI interfaceAlexey Kardashevskiy1-0/+8
2014-06-16spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy1-2/+5
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy1-0/+5
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
2014-04-08PPC: Clean up DECR implementationAlexander Graf1-2/+3
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-24/+24
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-8/+11
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+3
2013-12-20Add MSR VSX and Associated ExceptionTom Musta1-0/+5
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-1/+1
2013-09-02target-ppc: USE LPCR_ILE to control exception endian on POWER7Anton Blanchard1-0/+10
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-3/+6
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-3/+7
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-1/+1
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-7/+15
2013-01-07PPC: Bring EPR support closer to realityAlexander Graf1-0/+4
2013-01-07ppc/booke: fix crit/mcheck/debug exceptionsScott Wood1-9/+22
2012-10-31target-ppc: Pass PowerPCCPU to cpu_ppc_hypercallAndreas Färber1-2/+2
2012-10-31target-ppc: Pass PowerPCCPU to powerpc_excp()Andreas Färber1-16/+20
2012-06-24PPC: Add support for MSR_CMAlexander Graf1-4/+5
2012-06-24ppc: Move load and store helpers, switch to AREG0 free modeBlue Swirl1-1/+2
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-04 13:48:35 +0000