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path: root/target-ppc/helper.h
AgeCommit message (Expand)AuthorFilesLines
2016-11-15target-ppc: Implement bcdctz. instructionJose Ricardo Ziviani1-0/+1
2016-11-15target-ppc: Implement bcdcfz. instructionJose Ricardo Ziviani1-0/+1
2016-11-15target-ppc: Implement bcdctn. instructionJose Ricardo Ziviani1-0/+1
2016-11-15target-ppc: Implement bcdcfn. instructionJose Ricardo Ziviani1-0/+1
2016-11-15target-ppc: add vprtyb[w/d/q] instructionsAnkit Kumar1-0/+3
2016-11-15target-ppc: add vrldnm and vrlwnm instructionsBharata B Rao1-0/+2
2016-11-15target-ppc: add vrldnmi and vrlwmi instructionsGautham R. Shenoy1-0/+2
2016-10-28target-ppc: Add xvcmpnesp, xvcmpnedp instructionsSwapnil Bokade1-0/+2
2016-10-28target-ppc: add xscmp[eq,gt,ge,ne]dp instructionsSandipan Das1-0/+4
2016-10-28target-ppc: implement vnegw/d instructionsNikunj A Dadhania1-0/+2
2016-10-14target-ppc: implement vexts[bh]2w and vexts[bhw]2dNikunj A Dadhania1-0/+5
2016-10-05target-ppc: add vclzlsbb/vctzlsbb instructionsRajalakshmi Srinivasaraghavan1-0/+2
2016-10-05target-ppc: add vector compare not equal instructionsRajalakshmi Srinivasaraghavan1-0/+6
2016-09-23target-ppc: add flag in check_tlb_flush()Nikunj A Dadhania1-1/+2
2016-09-23target-ppc: implement darn instructionRavi Bangoria1-0/+2
2016-09-23target-ppc: add vector permute right indexed instructionRajalakshmi Srinivasaraghavan1-0/+1
2016-09-23target-ppc: add vector bit permute doubleword instructionRajalakshmi Srinivasaraghavan1-0/+1
2016-09-23target-ppc: add vector count trailing zeros instructionsRajalakshmi Srinivasaraghavan1-0/+4
2016-09-23target-ppc: add vector extract instructionsRajalakshmi Srinivasaraghavan1-0/+4
2016-09-23target-ppc: add vector insert instructionsRajalakshmi Srinivasaraghavan1-0/+4
2016-09-07ppc: Improve a few more helper flagsBenjamin Herrenschmidt1-7/+7
2016-09-07ppc: Improve the exception helpers flagsBenjamin Herrenschmidt1-2/+2
2016-09-07ppc: Improve flags for helpers loading/writing the time facilitiesBenjamin Herrenschmidt1-21/+21
2016-09-07target-ppc: add vsrv instructionVivek Andrew Sha1-0/+1
2016-09-07target-ppc: add vslv instructionVivek Andrew Sha1-0/+1
2016-09-07target-ppc: add vcmpnez[b,h,w][.] instructionsSwapnil Bokade1-0/+6
2016-09-07target-ppc: add vabsdu[b,h,w] instructionsSandipan Das1-0/+3
2016-09-07target-ppc: add dtstsfi[q] instructionsSandipan Das1-0/+2
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania1-0/+1
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania1-0/+1
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das1-0/+1
2016-07-01ppc: Initial HDEC supportBenjamin Herrenschmidt1-0/+2
2016-07-01ppc: Use a helper to filter writes to LPCRBenjamin Herrenschmidt1-0/+1
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-0/+1
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt1-0/+1
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt1-0/+1
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt1-0/+1
2016-01-30target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()David Gibson1-0/+1
2015-01-07target-ppc: Introduce tbeginTom Musta1-0/+2
2015-01-07target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta1-1/+1
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard1-2/+0
2014-09-08target-ppc: Implement mulldo with TCGTom Musta1-1/+0
2014-06-16target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy1-0/+1
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy1-0/+1
2014-06-16PPC: e500: Fix MMUCSR0 emulationAlex Zuepke1-1/+1
2014-06-16target-ppc: Introduce DFP Shift SignificandTom Musta1-0/+4
2014-06-16target-ppc: Introduce DFP Insert Biased ExponentTom Musta1-0/+2
2014-06-16target-ppc: Introduce DFP Extract Biased ExponentTom Musta1-0/+2
2014-06-16target-ppc: Introduce DFP Encode BCD to DPDTom Musta1-0/+2
2014-06-16target-ppc: Introduce DFP Decode DPD to BCDTom Musta1-0/+2
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