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AgeCommit message (Expand)AuthorFilesLines
2016-11-15target-ppc: Implement bcdctz. instructionJose Ricardo Ziviani1-0/+7
2016-11-15target-ppc: Implement bcdcfz. instructionJose Ricardo Ziviani1-0/+7
2016-11-15target-ppc: Implement bcdctn. instructionJose Ricardo Ziviani1-0/+4
2016-11-15target-ppc: Implement bcdcfn. instructionJose Ricardo Ziviani2-2/+57
2016-11-15target-ppc: add vprtyb[w/d/q] instructionsAnkit Kumar2-0/+7
2016-11-15target-ppc: add vrldnm and vrlwnm instructionsBharata B Rao2-2/+8
2016-11-15target-ppc: add vrldnmi and vrlwmi instructionsGautham R. Shenoy2-2/+8
2016-10-28target-ppc: Add xvcmpnesp, xvcmpnedp instructionsSwapnil Bokade2-0/+4
2016-10-28target-ppc: add xscmp[eq,gt,ge,ne]dp instructionsSandipan Das2-0/+8
2016-10-28target-ppc: add vmul10[u,eu,cu,ecu]q instructionsVasant Hegde2-4/+76
2016-10-28target-ppc: implement xxbr[qdwh] instructionNikunj A Dadhania2-0/+85
2016-10-28target-ppc: implement vnegw/d instructionsNikunj A Dadhania2-0/+4
2016-10-14target-ppc: implement vexts[bh]2w and vexts[bhw]2dNikunj A Dadhania2-0/+10
2016-10-05target-ppc: fix vmx instruction type/type2Nikunj A Dadhania2-24/+24
2016-10-05target-ppc: Implement mtvsrws instructionRavi Bangoria2-0/+20
2016-10-05target-ppc: add vclzlsbb/vctzlsbb instructionsRajalakshmi Srinivasaraghavan2-0/+16
2016-10-05target-ppc: add vector compare not equal instructionsRajalakshmi Srinivasaraghavan2-4/+13
2016-10-05target-ppc: add stxvb16x instructionNikunj A Dadhania2-0/+20
2016-10-05target-ppc: add lxvb16x instructionNikunj A Dadhania2-0/+20
2016-10-05target-ppc: add stxvh8x instructionNikunj A Dadhania2-0/+32
2016-10-05target-ppc: add lxvh8x instructionNikunj A Dadhania2-0/+50
2016-10-05target-ppc: improve stxvw4x implementationNikunj A Dadhania1-14/+19
2016-10-05target-ppc: improve lxvw4x implementationNikunj A Dadhania1-14/+18
2016-10-05target-ppc: Implement mtvsrdd instructionRavi Bangoria2-0/+24
2016-10-05target-ppc: Implement mfvsrld instructionRavi Bangoria2-0/+18
2016-09-23target-ppc: add stxsi[bh]x instructionNikunj A Dadhania2-0/+5
2016-09-23target-ppc: add lxsi[bw]zx instructionNikunj A Dadhania2-0/+4
2016-09-23target-ppc: add xxspltib instructionNikunj A Dadhania2-0/+25
2016-09-23target-ppc: convert st64 to use new macroNikunj A Dadhania5-32/+32
2016-09-23target-ppc: convert ld64 to use new macroNikunj A Dadhania4-32/+32
2016-09-23target-ppc: add vector permute right indexed instructionRajalakshmi Srinivasaraghavan2-0/+19
2016-09-23target-ppc: add vector bit permute doubleword instructionRajalakshmi Srinivasaraghavan2-0/+2
2016-09-23target-ppc: add vector count trailing zeros instructionsRajalakshmi Srinivasaraghavan2-0/+27
2016-09-23target-ppc: add vector extract instructionsRajalakshmi Srinivasaraghavan2-3/+17
2016-09-23target-ppc: add vector insert instructionsRajalakshmi Srinivasaraghavan2-5/+45
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt10-0/+0
2016-09-07target-ppc: add vsrv instructionVivek Andrew Sha2-0/+2
2016-09-07target-ppc: add vslv instructionVivek Andrew Sha2-0/+5
2016-09-07target-ppc: add vcmpnez[b,h,w][.] instructionsSwapnil Bokade2-0/+12
2016-09-07target-ppc: add vabsdu[b,h,w] instructionsSandipan Das2-3/+12
2016-09-07target-ppc: add dtstsfi[q] instructionsSandipan Das2-0/+34
2016-09-07ppc: Don't update the NIP in floating point generated codeBenjamin Herrenschmidt2-34/+0
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt2-0/+991
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt2-0/+1074
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt2-0/+363
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt2-0/+1334
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt2-0/+1209
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