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path: root/target-tricore/op_helper.c
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2015-06-29target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini1-2/+2
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann1-0/+49
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann1-0/+11
2015-05-11target-tricore: fix rfe not restoring the PCBastian Koppelmann1-0/+1
2015-05-11target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann1-1/+1
2015-04-04target-tricore: Fix check which was always falseStefan Weil1-1/+1
2015-03-24target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann1-30/+10
2015-03-24target-tricore: Fix two helper functions (clang warnings)Stefan Weil1-6/+6
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann1-0/+89
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann1-0/+84
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann1-0/+154
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann1-0/+109
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann1-0/+84
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann1-0/+153
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann1-0/+110
2015-03-03target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann1-6/+21
2015-01-27target-tricore: Add instructions of RRR opcode formatBastian Koppelmann1-0/+160
2015-01-26target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann1-15/+26
2015-01-26target-tricore: calculate av bits before saturationBastian Koppelmann1-12/+16
2015-01-26target-tricore: Several translator and cpu model fixesBastian Koppelmann1-0/+1
2015-01-26target-tricore: Add missing ULL suffix on 64 bit constantPeter Maydell1-1/+1
2014-12-21target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann1-0/+72
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...Bastian Koppelmann1-0/+195
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...Bastian Koppelmann1-0/+160
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...Bastian Koppelmann1-0/+525
2014-12-21target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann1-76/+58
2014-12-10target-tricore: Add instructions of RCR opcode formatBastian Koppelmann1-0/+168
2014-12-10target-tricore: Add instructions of RLC opcode formatBastian Koppelmann1-0/+11
2014-12-10target-tricore: Add instructions of RC opcode formatBastian Koppelmann1-0/+99
2014-10-20target-tricore: Add instructions of BO opcode formatBastian Koppelmann1-0/+36
2014-10-20target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann1-0/+45
2014-10-20target-tricore: Cleanup and BugfixesBastian Koppelmann1-26/+21
2014-09-01target-tricore: Add instructions of SR opcode formatBastian Koppelmann1-0/+52
2014-09-01target-tricore: Add instructions of SC opcode formatBastian Koppelmann1-0/+59
2014-09-01target-tricore: Add instructions of SB opcode formatBastian Koppelmann1-0/+180
2014-09-01target-tricore: Add instructions of SRR opcode formatBastian Koppelmann1-0/+43
2014-09-01target-tricore: Add softmmu supportBastian Koppelmann1-1/+32
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann1-0/+27