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2014-12-21target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann3-0/+273
2014-12-21target-tricore: Fix MFCR/MTCR insn and B format offset.Bastian Koppelmann2-2/+6
2014-12-21target-tricore: Add missing 1.6 insn of BOL opcode formatBastian Koppelmann2-1/+54
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...Bastian Koppelmann4-1/+390
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi...Bastian Koppelmann1-0/+97
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...Bastian Koppelmann3-0/+250
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...Bastian Koppelmann4-2/+942
2014-12-21target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann1-76/+58
2014-12-21target-tricore: Fix mask handling JNZ.T being 7 bit longBastian Koppelmann1-2/+2
2014-12-21target-tricore: pretty-print register dump and show more status registersAlex Zuepke1-6/+15
2014-12-21target-tricore: add missing 64-bit MOV in RLC formatAlex Zuepke2-0/+13
2014-12-21target-tricore: typo in BOL formatAlex Zuepke2-3/+3
2014-12-21target-tricore: fix offset masking in BOL formatAlex Zuepke1-1/+1
2014-12-10target-tricore: Add instructions of RCR opcode formatBastian Koppelmann4-1/+657
2014-12-10target-tricore: Add instructions of RLC opcode formatBastian Koppelmann5-0/+252
2014-12-10target-tricore: Add instructions of RCPW, RCRR and RCRW opcode formatBastian Koppelmann1-3/+129
2014-12-10target-tricore: Make TRICORE_FEATURES implying others.Bastian Koppelmann2-3/+12
2014-12-10target-tricore: Add instructions of RC opcode formatBastian Koppelmann4-0/+799
2014-12-10target-tricore: Add instructions of BRR opcode formatBastian Koppelmann2-2/+89
2014-12-10target-tricore: Add instructions of BRN opcode formatBastian Koppelmann2-0/+27
2014-12-10target-tricore: Add instructions of BRC opcode formatBastian Koppelmann2-3/+56
2014-12-10target-tricore: Add instructions of BOL opcode formatBastian Koppelmann2-1/+51
2014-10-20target-tricore: Add instructions of BO opcode formatBastian Koppelmann4-0/+704
2014-10-20target-tricore: Add instructions of BIT opcode formatBastian Koppelmann1-0/+312
2014-10-20target-tricore: Add instructions of B opcode formatBastian Koppelmann1-0/+27
2014-10-20target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann3-0/+352
2014-10-20target-tricore: Cleanup and BugfixesBastian Koppelmann2-27/+22
2014-09-25target-tricore: Remove the dummy interrupt boilerplateRichard Henderson4-8/+0
2014-09-01target-tricore: Add instructions of SR opcode formatBastian Koppelmann3-0/+164
2014-09-01target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann1-0/+121
2014-09-01target-tricore: Add instructions of SC opcode formatBastian Koppelmann3-0/+108
2014-09-01target-tricore: Add instructions of SBR opcode formatBastian Koppelmann1-1/+65
2014-09-01target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann1-0/+36
2014-09-01target-tricore: Add instructions of SB opcode formatBastian Koppelmann3-0/+276
2014-09-01target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann1-0/+59
2014-09-01target-tricore: Add instructions of SSR opcode formatBastian Koppelmann1-0/+50
2014-09-01target-tricore: Add instructions of SRR opcode formatBastian Koppelmann3-0/+211
2014-09-01target-tricore: Add instructions of SRC opcode formatBastian Koppelmann2-0/+267
2014-09-01target-tricore: Add masks and opcodes for decodingBastian Koppelmann2-0/+1407
2014-09-01target-tricore: Add initialization for translation and activate targetBastian Koppelmann1-0/+165
2014-09-01target-tricore: Add softmmu supportBastian Koppelmann2-2/+85
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann9-0/+916
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