peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2018-05-06	RISC-V: No traps on writes to misa,minstret,mcycle	Michael Clark	1	-12/+13
2018-05-06	RISC-V: Make mtvec/stvec ignore vectored traps	Michael Clark	1	-6/+8
2018-05-06	RISC-V: Add mcycle/minstret support for -icount auto	Michael Clark	1	-2/+26
2018-05-06	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	Michael Clark	1	-14/+48
2018-05-06	RISC-V: Allow S-mode mxr access when priv ISA >= v1.10	Michael Clark	1	-2/+5
2018-05-06	RISC-V: Hardwire satp to 0 for no-mmu case	Michael Clark	1	-2/+5
2018-03-29	RISC-V: Workaround for critical mstatus.FS bug	Michael Clark	1	-2/+15
2018-03-07	RISC-V CPU Helpers	Michael Clark	1	-0/+669