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AgeCommit message (Expand)AuthorFilesLines
2018-05-09target/sh4: convert to TranslatorOpsEmilio G. Cota1-85/+86
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-03-12qom: introduce object_class_get_list_sortedPaolo Bonzini1-14/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée3-2/+2
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-2/+2
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier3-6/+6
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-2/+2
2017-12-18target/sh4: Convert to DisasContextBaseRichard Henderson1-76/+78
2017-12-18target/sh4: Do not singlestep after exceptionsRichard Henderson1-16/+16
2017-12-18target/sh4: Convert to DisasJumpTypeRichard Henderson1-35/+30
2017-12-18target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson3-23/+64
2017-12-18target/sh4: fix TCG leak during gusa sequenceAlex Bennée1-1/+1
2017-12-18target/sh4: add missing tcg_temp_free() in _decode_opc()Philippe Mathieu-Daudé1-0/+2
2017-12-18Remove empty statementsLadi Prosek1-1/+1
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell3-72/+46
2017-10-27sh4: remove SuperHCPUClass::name fieldIgor Mammedov2-9/+3
2017-10-27sh4: simplify superh_cpu_class_by_name()Igor Mammedov1-22/+12
2017-10-27sh4: cleanup cpu type name compositionIgor Mammedov3-41/+31
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/sh4: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson2-11/+1
2017-10-16linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31Richard Henderson1-1/+5
2017-10-10tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota1-2/+2
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-3/+0
2017-09-01sh4: replace cpu_sh4_init() with cpu_generic_init()Igor Mammedov2-7/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-18target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson1-10/+20
2017-07-18target/sh4: Implement fsrraRichard Henderson3-0/+19
2017-07-18target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson1-0/+2
2017-07-18target/sh4: Implement fpchgRichard Henderson1-0/+5
2017-07-18target/sh4: Introduce CHECK_SH4ARichard Henderson1-34/+30
2017-07-18target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson1-26/+31
2017-07-18target/sh4: Tidy misc illegal insn checksRichard Henderson1-9/+13
2017-07-18target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson1-10/+14
2017-07-18target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson1-10/+4
2017-07-18target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson1-6/+5
2017-07-18target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson1-4/+4
2017-07-18target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson1-39/+36
2017-07-18target/sh4: Merge DREG into fpr64 routinesRichard Henderson1-11/+15
2017-07-18target/sh4: Eliminate unused XREG macroRichard Henderson1-1/+0
2017-07-18target/sh4: Hoist fp register bank selectionRichard Henderson1-3/+5
2017-07-18target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson1-13/+13
2017-07-18target/sh4: Unify cpu_fregs into FREGRichard Henderson1-73/+52
2017-07-18target/sh4: Hoist register bank selectionRichard Henderson1-10/+11
2017-07-18target/sh4: Recognize common gUSA sequencesRichard Henderson1-0/+321
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