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path: root/target/sparc/ldst_helper.c
AgeCommit message (Expand)AuthorFilesLines
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-3/+3
2017-09-01sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov1-7/+7
2017-02-24cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée1-3/+5
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko1-8/+44
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko1-0/+31
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko1-0/+22
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko1-36/+15
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko1-22/+102
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko1-4/+4
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko1-2/+4
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko1-0/+1
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko1-14/+18
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko1-0/+24
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko1-3/+2
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko1-12/+54
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko1-2/+13
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée1-6/+6
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+1709