| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-02-16 | target-i386: correctly propagate retaddr into SVM helpers | Paolo Bonzini | 6 | -57/+55 |
| 2017-02-16 | report guest crash information in GUEST_PANICKED event | Anton Nefedov | 2 | -2/+3 |
| 2017-02-16 | i386/cpu: add crash-information QOM property | Anton Nefedov | 1 | -0/+50 |
| 2017-02-14 | Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into staging | Peter Maydell | 14 | -939/+857 |
| 2017-02-14 | target/openrisc: Optimize for r0 being zero | Richard Henderson | 3 | -23/+66 |
| 2017-02-14 | target/openrisc: Tidy handling of delayed branches | Richard Henderson | 5 | -35/+25 |
| 2017-02-14 | target/openrisc: Tidy ppc/npc implementation | Richard Henderson | 6 | -55/+39 |
| 2017-02-14 | target/openrisc: Optimize l.jal to next | Richard Henderson | 1 | -1/+5 |
| 2017-02-14 | target/openrisc: Fix madd | Richard Henderson | 4 | -61/+30 |
| 2017-02-14 | target/openrisc: Implement muld, muldu, macu, msbu | Richard Henderson | 1 | -0/+108 |
| 2017-02-14 | target/openrisc: Represent MACHI:MACLO as a single unit | Richard Henderson | 4 | -61/+80 |
| 2017-02-14 | target/openrisc: Implement msync | Richard Henderson | 1 | -0/+1 |
| 2017-02-14 | target/openrisc: Enable trap, csync, msync, psync for user mode | Richard Henderson | 1 | -32/+0 |
| 2017-02-14 | target/openrisc: Set flags on helpers | Richard Henderson | 1 | -12/+12 |
| 2017-02-14 | target/openrisc: Use movcond where appropriate | Richard Henderson | 1 | -14/+14 |
| 2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson | 4 | -89/+78 |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 7 | -74/+96 |
| 2017-02-14 | target/openrisc: Invert the decoding in dec_calc | Richard Henderson | 1 | -207/+95 |
| 2017-02-14 | target/openrisc: Put SR[OVE] in TB flags | Richard Henderson | 3 | -12/+18 |
| 2017-02-14 | target/openrisc: Streamline arithmetic and OVE | Richard Henderson | 5 | -314/+191 |
| 2017-02-14 | target/openrisc: Rationalize immediate extraction | Richard Henderson | 1 | -58/+40 |
| 2017-02-14 | target/openrisc: Tidy insn dumping | Richard Henderson | 1 | -24/+12 |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson | 7 | -8/+81 |
| 2017-02-14 | target/openrisc: Fix exception handling status registers | Stafford Horne | 1 | -0/+7 |
| 2017-02-14 | target/openrisc: Rename the cpu from or32 to or1k | Richard Henderson | 1 | -1/+1 |
| 2017-02-13 | migration: consolidate VMStateField.start | Halil Pasic | 1 | -1/+1 |
| 2017-02-10 | target-arm: Enable vPMU support under TCG mode | Wei Huang | 2 | -7/+2 |
| 2017-02-10 | target-arm: Add support for PMU register PMINTENSET_EL1 | Wei Huang | 2 | -2/+10 |
| 2017-02-10 | target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 | Wei Huang | 2 | -6/+25 |
| 2017-02-10 | target-arm: Add support for PMU register PMSELR_EL0 | Wei Huang | 2 | -6/+22 |
| 2017-02-07 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts | Peter Maydell | 3 | -63/+149 |
| 2017-02-07 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode | Peter Maydell | 1 | -3/+6 |
| 2017-02-07 | arm: Correctly handle watchpoints for BE32 CPUs | Julian Brown | 3 | -0/+30 |
| 2017-02-07 | Fix Thumb-1 BE32 execution and disassembly. | Julian Brown | 2 | -1/+32 |
| 2017-02-07 | target/arm: Add cfgend parameter for ARM CPU selection. | Julian Brown | 2 | -0/+20 |
| 2017-02-06 | target/hppa: Fix gdb_write_register | Richard Henderson | 1 | -0/+1 |
| 2017-02-06 | target/hppa: Tidy do_cbranch | Richard Henderson | 1 | -12/+5 |
| 2017-02-02 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into... | Peter Maydell | 24 | -476/+2421 |
| 2017-02-02 | ppc/kvm: Handle the "family" CPU via alias instead of registering new types | Thomas Huth | 1 | -13/+23 |
| 2017-02-02 | target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation | Suraj Jitindar Singh | 1 | -1/+1 |
| 2017-02-02 | target/ppc/mmu_hash64: Fix printing unsigned as signed int | Suraj Jitindar Singh | 1 | -2/+2 |
| 2017-02-02 | tcg/POWER9: NOOP the cp_abort instruction | Suraj Jitindar Singh | 1 | -0/+5 |
| 2017-02-02 | target/ppc/debug: Print LPCR register value if register exists | Suraj Jitindar Singh | 1 | -0/+3 |
| 2017-02-02 | target-ppc: Add xststdc[sp, dp, qp] instructions | Nikunj A Dadhania | 5 | -8/+69 |
| 2017-02-02 | target-ppc: Add xvtstdc[sp,dp] instructions | Nikunj A Dadhania | 5 | -2/+55 |
| 2017-02-01 | arm: add trailing ; after MISMATCH_CHECK | Michael S. Tsirkin | 1 | -49/+49 |
| 2017-02-01 | arm: better stub version for MISMATCH_CHECK | Michael S. Tsirkin | 1 | -1/+3 |
| 2017-01-31 | target/ppc/cpu-models: Fix/remove bad CPU aliases | Thomas Huth | 1 | -20/+2 |
| 2017-01-31 | target/ppc: Remove unused POWERPC_FAMILY(POWER) | Thomas Huth | 1 | -22/+0 |
| 2017-01-31 | spapr: clock should count only if vm is running | Laurent Vivier | 1 | -0/+3 |
