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Diffstat (limited to 'chip_design/generate-chipdesign.py')
-rwxr-xr-x | chip_design/generate-chipdesign.py | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/chip_design/generate-chipdesign.py b/chip_design/generate-chipdesign.py index 862053e..d834078 100755 --- a/chip_design/generate-chipdesign.py +++ b/chip_design/generate-chipdesign.py @@ -104,6 +104,21 @@ for i in range(len(powers)): ] preds += ['(or %s)' % ' '.join(fillin(altpreds, vars()))] +# Require that each component is attached to power resource +for i in range(len(powers), len(all_components)): + altpreds = [] + for j in range(len(powers)): + # Power (j) top/right side hits component (i) bottom/left side or + # Power (j) bottom/left side hits component (i) top/right side. + # (note: copied from above overlap check with '>='/'<=' -> '='.) + altpreds += fillin([ + '(= (+ y{j} h{j}) y{i})', + '(= (+ x{j} w{j}) x{i})', + '(= y{j} (+ y{i} h{i}))', + '(= x{j} (+ x{i} w{i}))', + ], vars()) + preds += ['(or %s)' % ' \n'.join(altpreds)] + # Begin generator s = """(benchmark test.smt :logic QF_UFLIA |