diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-01-22 19:53:49 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-09 10:55:27 +0000 |
| commit | 1db5e96c54d8b3d1df0a6fed6771390be6b010da (patch) | |
| tree | 1fa2705e48e28a87f16165cdeca6e6af106b9fbd /target/arm/translate-a64.c | |
| parent | 5be5e8eda78474f6e89a54af12ee6f44234115ed (diff) | |
| download | qemu-1db5e96c54d8b3d1df0a6fed6771390be6b010da.tar.gz | |
target/arm: Add SVE state to TB->FLAGS
Add both SVE exception state and vector length.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180123035349.24538-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 352a79bad1..fb1a4cb532 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12058,6 +12058,8 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); + dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; |