peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2018-05-09	translator: merge max_insns into DisasContextBase	Emilio G. Cota	1	-5/+3
2018-05-04	target/arm: Tidy condition in disas_simd_two_reg_misc	Richard Henderson	1	-1/+5
2018-05-04	target/arm: Tidy conditions in handle_vec_simd_shri	Richard Henderson	1	-5/+1
2018-04-26	target/arm: Allow EL change hooks to do IO	Aaron Lindsay	1	-0/+6
2018-03-23	target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK	Peter Maydell	1	-2/+13
2018-03-23	arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT	Victor Kamensky	1	-3/+3
2018-03-02	target/arm: Decode aa64 armv8.3 fcmla	Richard Henderson	1	-8/+86
2018-03-02	target/arm: Decode aa64 armv8.3 fcadd	Richard Henderson	1	-1/+47
2018-03-02	target/arm: Decode aa64 armv8.1 scalar/vector x indexed element	Richard Henderson	1	-0/+29
2018-03-02	target/arm: Decode aa64 armv8.1 three same extra	Richard Henderson	1	-0/+83
2018-03-02	target/arm: Decode aa64 armv8.1 scalar three same extra	Richard Henderson	1	-0/+84
2018-03-02	target/arm: Refactor disas_simd_indexed size checks	Richard Henderson	1	-31/+30
2018-03-02	target/arm: Refactor disas_simd_indexed decode	Richard Henderson	1	-66/+59
2018-03-01	arm/translate-a64: add all single op FP16 to handle_fp_1src_half	Alex Bennée	1	-0/+71
2018-03-01	arm/translate-a64: implement simd_scalar_three_reg_same_fp16	Alex Bennée	1	-0/+99
2018-03-01	arm/translate-a64: add all FP16 ops in simd_scalar_pairwise	Alex Bennée	1	-26/+54
2018-03-01	arm/translate-a64: add FP16 FMOV to simd_mod_imm	Alex Bennée	1	-10/+25
2018-03-01	arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+7
2018-03-01	arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+5
2018-03-01	arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+4
2018-03-01	arm/translate-a64: add FP16 FRECPE	Alex Bennée	1	-0/+8
2018-03-01	arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16	Alex Bennée	1	-1/+15
2018-03-01	arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16	Alex Bennée	1	-24/+90
2018-03-01	arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16	Alex Bennée	1	-23/+57
2018-03-01	arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16	Alex Bennée	1	-1/+84
2018-03-01	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	Alex Bennée	1	-5/+118
2018-03-01	arm/translate-a64: initial decode for simd_two_reg_misc_fp16	Alex Bennée	1	-0/+40
2018-03-01	arm/translate-a64: add FP16 x2 ops for simd_indexed	Alex Bennée	1	-5/+21
2018-03-01	arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed	Alex Bennée	1	-16/+66
2018-03-01	arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16	Alex Bennée	1	-75/+133
2018-03-01	arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16	Alex Bennée	1	-0/+6
2018-03-01	arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16	Alex Bennée	1	-0/+15
2018-03-01	arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16	Alex Bennée	1	-0/+15
2018-03-01	arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16	Alex Bennée	1	-0/+28
2018-03-01	arm/translate-a64: initial decode for simd_three_reg_same_fp16	Alex Bennée	1	-0/+73
2018-03-01	arm/translate-a64: handle_3same_64 comment fix	Alex Bennée	1	-2/+1
2018-03-01	arm/translate-a64: implement half-precision F(MIN\|MAX)(V\|NMV)	Alex Bennée	1	-54/+88
2018-03-01	target/arm/helper: pass explicit fpst to set_rmode	Alex Bennée	1	-13/+13
2018-03-01	target/arm/cpu.h: add additional float_status flags	Alex Bennée	1	-24/+29
2018-02-15	target/arm: Handle SVE registers when using clear_vec_high	Richard Henderson	1	-100/+62
2018-02-15	target/arm: Enforce access to ZCR_EL at translation	Richard Henderson	1	-0/+16
2018-02-15	target/arm: Enforce FP access to FPCR/FPSR	Richard Henderson	1	-0/+3
2018-02-09	target/arm: Add SVE state to TB->FLAGS	Richard Henderson	1	-0/+2
2018-02-09	target/arm: Expand vector registers for SVE	Richard Henderson	1	-4/+4
2018-02-09	target/arm: implement SM4 instructions	Ard Biesheuvel	1	-0/+8
2018-02-09	target/arm: implement SM3 instructions	Ard Biesheuvel	1	-3/+85
2018-02-09	target/arm: implement SHA-3 instructions	Ard Biesheuvel	1	-4/+144
2018-02-09	target/arm: implement SHA-512 instructions	Ard Biesheuvel	1	-0/+110
2018-02-08	target/arm: Use vector infrastructure for aa64 orr/bic immediate	Richard Henderson	1	-23/+5
2018-02-08	target/arm: Use vector infrastructure for aa64 multiplies	Richard Henderson	1	-25/+129