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| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 12:22:12 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-09-06 08:06:47 -0700 |
| commit | a68956ad7f8510bdc0b54793c65c62c6a94570a4 (patch) | |
| tree | 7aa551a7bfeaae1d1aaad5bbcd8890b4611f4f57 /target/arm/translate-a64.c | |
| parent | f62bd897e64c6fb1f93e8795e835980516fe53b5 (diff) | |
| download | qemu-a68956ad7f8510bdc0b54793c65c62c6a94570a4.tar.gz | |
target/arm: [tcg,a64] Port to insn_start
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan>
[rth: Use DISAS_TOO_MANY for "execute only one more" after bp.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e8dc96c28a..1eab10696c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11259,6 +11259,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, return max_insns; } +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11290,8 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; |