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| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 12:34:18 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-09-06 08:06:47 -0700 |
| commit | 13189a9080b35b13af23f2be4806fa0cdbb31af3 (patch) | |
| tree | 08f0fc8c57c5c472fbcab8dd2c00ee07714bd321 /target/arm/translate.h | |
| parent | 0cb56b373da70047979b61b042f59aaff4012e1b (diff) | |
| download | qemu-13189a9080b35b13af23f2be4806fa0cdbb31af3.tar.gz | |
target/arm: [tcg] Port to translate_insn
Incrementally paves the way towards using the generic instruction translation
loop.
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan>
[rth: Adjust for translate_insn interface change.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index a804ff65ac..e8dcec51ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; |