summaryrefslogtreecommitdiff
path: root/target/microblaze/translate.c
diff options
context:
space:
mode:
authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2017-06-15 16:28:35 +0200
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2017-07-04 09:22:20 +0200
commitd09b2585f2ffadfb7e8c333de6f12290a80f9b6c (patch)
tree5421f2497dd9bcc941343f63154cd774c46f5153 /target/microblaze/translate.c
parentfaa48d742c2133ec1795d2086be14178c785024a (diff)
downloadqemu-d09b2585f2ffadfb7e8c333de6f12290a80f9b6c.tar.gz
target-microblaze: dec_barrel: Add BSIFI
Add support for BSIFI. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze/translate.c')
-rw-r--r--target/microblaze/translate.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 3fad13c719..cb65d1e129 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -661,7 +661,7 @@ static void dec_barrel(DisasContext *dc)
{
TCGv t0;
unsigned int imm_w, imm_s;
- bool s, t, e = false;
+ bool s, t, e = false, i = false;
if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
@@ -673,6 +673,7 @@ static void dec_barrel(DisasContext *dc)
if (dc->type_b) {
/* Insert and extract are only available in immediate mode. */
+ i = extract32(dc->imm, 15, 1);
e = extract32(dc->imm, 14, 1);
}
s = extract32(dc->imm, 10, 1);
@@ -692,6 +693,17 @@ static void dec_barrel(DisasContext *dc)
} else {
tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
}
+ } else if (i) {
+ int width = imm_w - imm_s + 1;
+
+ if (imm_w < imm_s) {
+ /* These inputs have an undefined behavior. */
+ qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n",
+ imm_w, imm_s);
+ } else {
+ tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra],
+ imm_s, width);
+ }
} else {
t0 = tcg_temp_new();