diff options
| author | Richard Henderson <rth@twiddle.net> | 2017-07-18 10:02:38 -1000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-18 23:39:17 +0200 |
| commit | 5c13bad9ecf758946877d041bb3b9fd012f4503a (patch) | |
| tree | 5e35c6989b4ef0ffc1103e213ca19d42fdecd826 /target/sh4/translate.c | |
| parent | e5d8053e76bda79744710e5b59e70f9fcbce7df7 (diff) | |
| download | qemu-5c13bad9ecf758946877d041bb3b9fd012f4503a.tar.gz | |
target/sh4: Hoist fp register bank selection
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-14-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/sh4/translate.c')
| -rw-r--r-- | target/sh4/translate.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b706a6a153..bc6f33970b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -42,6 +42,7 @@ typedef struct DisasContext { int bstate; int memidx; int gbank; + int fbank; uint32_t delayed_pc; int singlestep_enabled; uint32_t features; @@ -353,12 +354,12 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) #define REG(x) cpu_gregs[(x) ^ ctx->gbank] #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10] +#define FREG(x) cpu_fregs[(x) ^ ctx->fbank] -#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -#define XREG(x) FREG(XHACK(x)) +#define XREG(x) FREG(XHACK(x)) /* Assumes lsb of (x) is always 0 */ -#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)) +#define DREG(x) ((x) ^ ctx->fbank) #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -2232,6 +2233,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA); ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) && (ctx.tbflags & (1 << SR_RB))) * 0x10; + ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { |