peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2018-05-09	target/sh4: convert to TranslatorOps	Emilio G. Cota	1	-85/+86
2017-12-29	tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*	Richard Henderson	1	-2/+2
2017-12-18	target/sh4: Convert to DisasContextBase	Richard Henderson	1	-76/+78
2017-12-18	target/sh4: Do not singlestep after exceptions	Richard Henderson	1	-16/+16
2017-12-18	target/sh4: Convert to DisasJumpType	Richard Henderson	1	-35/+30
2017-12-18	target/sh4: Use cmpxchg for movco when parallel_cpus	Richard Henderson	1	-22/+60
2017-12-18	target/sh4: fix TCG leak during gusa sequence	Alex Bennée	1	-1/+1
2017-12-18	target/sh4: add missing tcg_temp_free() in _decode_opc()	Philippe Mathieu-Daudé	1	-0/+2
2017-12-18	Remove empty statements	Ladi Prosek	1	-1/+1
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-4/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	target/sh4: check CF_PARALLEL instead of parallel_cpus	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-3/+3
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-7/+0
2017-10-10	tcg: remove addr argument from lookup_tb_ptr	Emilio G. Cota	1	-2/+2
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-18	target/sh4: Use tcg_gen_lookup_and_goto_ptr	Richard Henderson	1	-10/+20
2017-07-18	target/sh4: Implement fsrra	Richard Henderson	1	-0/+2
2017-07-18	target/sh4: Add missing FPSCR.PR == 0 checks	Richard Henderson	1	-0/+2
2017-07-18	target/sh4: Implement fpchg	Richard Henderson	1	-0/+5
2017-07-18	target/sh4: Introduce CHECK_SH4A	Richard Henderson	1	-34/+30
2017-07-18	target/sh4: Introduce CHECK_FPSCR_PR_*	Richard Henderson	1	-26/+31
2017-07-18	target/sh4: Tidy misc illegal insn checks	Richard Henderson	1	-9/+13
2017-07-18	target/sh4: Unify code for CHECK_FPU_ENABLED	Richard Henderson	1	-10/+14
2017-07-18	target/sh4: Unify code for CHECK_PRIVILEGED	Richard Henderson	1	-10/+4
2017-07-18	target/sh4: Unify code for CHECK_NOT_DELAY_SLOT	Richard Henderson	1	-6/+5
2017-07-18	target/sh4: Simplify 64-bit fp reg-reg move	Richard Henderson	1	-4/+4
2017-07-18	target/sh4: Load/store Dr as 64-bit quantities	Richard Henderson	1	-39/+36
2017-07-18	target/sh4: Merge DREG into fpr64 routines	Richard Henderson	1	-11/+15
2017-07-18	target/sh4: Eliminate unused XREG macro	Richard Henderson	1	-1/+0
2017-07-18	target/sh4: Hoist fp register bank selection	Richard Henderson	1	-3/+5
2017-07-18	target/sh4: Pass DisasContext to fpr64 routines	Richard Henderson	1	-13/+13
2017-07-18	target/sh4: Unify cpu_fregs into FREG	Richard Henderson	1	-73/+52
2017-07-18	target/sh4: Hoist register bank selection	Richard Henderson	1	-10/+11
2017-07-18	target/sh4: Recognize common gUSA sequences	Richard Henderson	1	-0/+321
2017-07-18	target/sh4: Handle user-space atomics	Richard Henderson	1	-12/+126
2017-07-18	target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK	Richard Henderson	1	-2/+2
2017-07-18	target/sh4: Consolidate end-of-TB tests	Richard Henderson	1	-14/+17
2017-07-18	target/sh4: return result of fcmp using TCG	Aurelien Jarno	1	-4/+6
2017-07-18	target/sh4: do not use a helper to implement fneg	Aurelien Jarno	1	-3/+2
2017-07-18	target/sh4: do not check for PR bit for fabs instruction	Aurelien Jarno	1	-12/+3
2017-05-30	target/sh4: fix RTE instruction delay slot	Aurelien Jarno	1	-2/+6
2017-05-30	target/sh4: introduce DELAY_SLOT_MASK	Aurelien Jarno	1	-9/+8
2017-05-13	target/sh4: trap unaligned accesses	Aurelien Jarno	1	-2/+4
2017-05-13	target/sh4: movua.l is an SH4-A only instruction	Aurelien Jarno	1	-11/+15
2017-05-13	target/sh4: implement tas.b using atomic helper	Aurelien Jarno	1	-12/+7
2017-05-13	target/sh4: generate fences for SH4	Aurelien Jarno	1	-4/+5
2017-05-13	target/sh4: optimize gen_write_sr using extract op	Aurelien Jarno	1	-6/+3