peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-5/+5
2017-09-21	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé	1	-0/+1
2017-08-02	target-mips: apply CP0.PageMask before writing into TLB entry	Leon Alrae	1	-2/+3
2017-07-20	target/mips: Add segmentation control registers	James Hogan	1	-0/+24
2017-07-20	target/mips: Add an MMU mode for ERL	James Hogan	1	-0/+10
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan	1	-2/+2
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	1	-2/+10
2017-07-20	target/mips: Weaken TLB flush on UX,SX,KX,ASID changes	James Hogan	1	-1/+1
2017-07-20	target/mips: Fix TLBWI shadow flush for EHINV,XI,RI	James Hogan	1	-2/+10
2017-03-09	target/mips: hold BQL for timer interrupts	Yongbok Kim	1	-3/+18
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-4/+4
2017-01-10	target-mips: Use clz opcode	Richard Henderson	1	-22/+0
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+4196