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path: root/target/xtensa/translate.c
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2018-05-09target/xtensa: avoid integer overflow in next_page PC checkEmilio G. Cota1-5/+4
2018-03-16target/xtensa: add linux-user supportMax Filippov1-6/+37
2018-03-13target/xtensa: support MTTCGMax Filippov1-15/+31
2018-03-13target/xtensa: mark register windows in the dumpMax Filippov1-2/+7
2018-03-13target/xtensa: dump correct physical registersMax Filippov1-0/+1
2018-01-24Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell1-2/+2
2018-01-22target/xtensa: disas/xtensa: fix coverity warningsMax Filippov1-2/+2
2018-01-12target/xtensa: Remove duplicate typedef of DisasContextPeter Maydell1-2/+2
2018-01-09target/xtensa: implement const16Max Filippov1-0/+14
2018-01-09target/xtensa: implement GPIO32Max Filippov1-0/+53
2018-01-09target/xtensa: implement salt/saltuMax Filippov1-0/+18
2018-01-09target/xtensa: add internal/noop SRs and opcodesMax Filippov1-0/+33
2018-01-09target/xtensa: drop DisasContext::litbaseMax Filippov1-22/+5
2018-01-09target/xtensa: use libisa for instruction decodingMax Filippov1-2144/+84
2017-12-18target/xtensa: extract FPU2000 opcode translatorsMax Filippov1-0/+374
2017-12-18target/xtensa: extract core opcode translatorsMax Filippov1-0/+3121
2017-12-18target/xtensa: pass actual frame size to the entry helperMax Filippov1-1/+1
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-3/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-14/+14
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-0/+4
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-01-25Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell1-78/+167
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov1-2/+10
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov1-0/+8
2017-01-15target/xtensa: don't continue translation after exceptionMax Filippov1-1/+4
2017-01-15target/xtensa: support icountMax Filippov1-45/+134
2017-01-15target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov1-31/+12
2017-01-10target-xtensa: Use clrsb helperRichard Henderson1-10/+1
2017-01-10target-xtensa: Use clz opcodeRichard Henderson1-2/+11
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+3225