peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2018-05-09	target/mips: convert to TranslatorOps	Emilio G. Cota	1	-114/+113
2018-05-09	target/mips: use *ctx for DisasContext	Emilio G. Cota	1	-82/+83
2018-05-09	target/mips: convert to DisasContextBase	Emilio G. Cota	1	-171/+175
2018-05-09	target/mips: convert to DisasJumpType	Emilio G. Cota	1	-95/+91
2018-05-09	target/mips: use lookup_and_goto_ptr on BS_STOP	Emilio G. Cota	1	-1/+2
2018-05-09	target/mips: avoid integer overflow in next_page PC check	Emilio G. Cota	1	-3/+3
2017-12-29	tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*	Richard Henderson	1	-1/+1
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	1	-14/+6
2017-10-27	mips: malta/boston: replace cpu_model with cpu_type	Igor Mammedov	1	-14/+6
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	1	-1/+1
2017-10-25	disas: Remove unused flags arguments	Richard Henderson	1	-1/+1
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-4/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-13/+13
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	1	-7/+0
2017-10-10	tcg: remove addr argument from lookup_tb_ptr	Emilio G. Cota	1	-2/+2
2017-09-21	mips: replace cpu_mips_init() with cpu_generic_init()	Igor Mammedov	1	-17/+0
2017-09-21	mips: MIPSCPU model subclasses	Igor Mammedov	1	-7/+6
2017-09-21	mips: call cpu_mips_realize_env() from mips_cpu_realizefn()	Philippe Mathieu-Daudé	1	-1/+0
2017-09-21	mips: split cpu_mips_realize_env() out of cpu_mips_init()	Philippe Mathieu-Daudé	1	-7/+12
2017-09-21	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé	1	-0/+1
2017-08-02	target/mips: Fix RDHWR CC with icount	James Hogan	1	-0/+11
2017-08-02	target/mips: Drop redundant gen_io_start/stop()	James Hogan	1	-8/+0
2017-08-02	target/mips: Use BS_EXCP where interrupts are expected	James Hogan	1	-13/+34
2017-08-02	mips: Add KVM T&E segment support for TCG	James Hogan	1	-2/+2
2017-08-02	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	James Hogan	1	-4/+0
2017-07-20	target/mips: Add segmentation control registers	James Hogan	1	-0/+88
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan	1	-1/+1
2017-07-20	target/mips: Decode microMIPS EVA load & store instructions	James Hogan	1	-4/+115
2017-07-20	target/mips: Decode MIPS32 EVA load & store instructions	James Hogan	1	-0/+106
2017-07-20	target/mips: Prepare loads/stores for EVA	James Hogan	1	-35/+42
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	1	-3/+5
2017-07-20	target/mips: Fix MIPS64 MFC0 UserLocal on BE host	James Hogan	1	-2/+3
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-17	target/mips: optimize WSBH, DSBH and DSHD	Aurelien Jarno	1	-6/+12
2017-07-11	target/mips: fix msa copy_[s\|u]_df rd = 0 corner case	Miodrag Dinic	1	-2/+6
2017-06-05	target/mips: optimize indirect branches	Aurelien Jarno	1	-1/+1
2017-06-05	target/mips: optimize cross-page direct jumps in softmmu	Aurelien Jarno	1	-1/+1
2017-03-20	target/mips: fix delay slot detection in gen_msa_branch()	Yongbok Kim	1	-1/+1
2017-03-20	target-mips: replace few LOG_DISAS() with trace points	Philippe Mathieu-Daudé	1	-14/+11
2017-03-20	target-mips: replace break by goto cp0_unimplemented	Philippe Mathieu-Daudé	1	-44/+44
2017-03-20	target-mips: log bad coprocessor0 register accesses with LOG_UNIMP	Philippe Mathieu-Daudé	1	-6/+6
2017-03-20	target-mips: remove old & unuseful comments	Philippe Mathieu-Daudé	1	-4/+0
2017-02-21	target-mips: Provide function to test if a CPU supports an ISA	Paul Burton	1	-0/+10
2017-01-10	target-mips: Use clz opcode	Richard Henderson	1	-7/+16
2017-01-10	target-mips: Use the new extract op	Richard Henderson	1	-7/+5
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+20423